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Sat, 05 Apr 2025 02:14:20 -0700 (PDT) Received: from [192.168.68.110] ([177.170.227.223]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-739d97d1881sm4834066b3a.3.2025.04.05.02.14.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 05 Apr 2025 02:14:19 -0700 (PDT) Message-ID: <87129ffe-fa62-4e6d-b154-8e61a22ce13a@ventanamicro.com> Date: Sat, 5 Apr 2025 06:14:15 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 04/12] target/riscv: rvv: Apply vext_check_input_eew to vector register gather instructions To: Max Chou , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , antonb@tenstorrent.com References: <20250329144446.2619306-1-max.chou@sifive.com> <20250329144446.2619306-5-max.chou@sifive.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20250329144446.2619306-5-max.chou@sifive.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 3/29/25 11:44 AM, Max Chou wrote: > Handle the overlap of source registers with different EEWs. > The vs1 EEW of vrgatherei16.vv is 16. > > Co-authored-by: Anton Blanchard > Co-authored-by: Max Chou Since you're marked as Author you don't need this co-authored-by tag in your name too. Same thing for patches 5 to 11. > Signed-off-by: Max Chou > --- With the co-authored-by tag removed: Reviewed-by: Daniel Henrique Barboza > target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index 70c19c49ae4..4a0c9fbeff3 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -3478,6 +3478,7 @@ static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a) > { > return require_rvv(s) && > vext_check_isa_ill(s) && > + vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew, a->vm) && > require_align(a->rd, s->lmul) && > require_align(a->rs1, s->lmul) && > require_align(a->rs2, s->lmul) && > @@ -3490,6 +3491,7 @@ static bool vrgatherei16_vv_check(DisasContext *s, arg_rmrr *a) > int8_t emul = MO_16 - s->sew + s->lmul; > return require_rvv(s) && > vext_check_isa_ill(s) && > + vext_check_input_eew(s, a->rs1, MO_16, a->rs2, s->sew, a->vm) && > (emul >= -3 && emul <= 3) && > require_align(a->rd, s->lmul) && > require_align(a->rs1, emul) && > @@ -3509,6 +3511,7 @@ static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a) > { > return require_rvv(s) && > vext_check_isa_ill(s) && > + vext_check_input_eew(s, -1, MO_64, a->rs2, s->sew, a->vm) && > require_align(a->rd, s->lmul) && > require_align(a->rs2, s->lmul) && > (a->rd != a->rs2) &&