From: Thomas Gleixner <tglx@kernel.org>
To: Icenowy Zheng <zhengxingda@iscas.ac.cn>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Huacai Chen <chenhuacai@kernel.org>,
Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Yao Zi <me@ziyao.cc>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-mips@vger.kernel.org,
Icenowy Zheng <zhengxingda@iscas.ac.cn>,
linux-s390@vger.kernel.org, Heiko Carstens <hca@linux.ibm.com>,
Vasily Gorbik <gor@linux.ibm.com>,
Alexander Gordeev <agordeev@linux.ibm.com>
Subject: Re: [PATCH v2 1/7] genirq: reserve NR_IRQS_LEGACY IRQs in dynirq by default
Date: Wed, 11 Feb 2026 12:51:54 +0100 [thread overview]
Message-ID: <871pira46d.ffs@tglx> (raw)
In-Reply-To: <20260211094408.3463916-2-zhengxingda@iscas.ac.cn>
On Wed, Feb 11 2026 at 17:44, Icenowy Zheng wrote:
> Several architectures define NR_IRQS_LEGACY to reserve a low range of IRQ
> numbers for fixed legacy allocations (e.g. ISA interrupts) which should
> not be handed out by the dynamic IRQ allocator.
>
> arch_dynirq_lower_bound() exists to enforce this, but today only x86 wires
> it up. In the current boot order this typically works because legacy IRQ
> domains register early and claim the low IRQ numbers first; however, that
> assumption breaks if the legacy controller is probed later.
>
> Make the default arch_dynirq_lower_bound() implementation honour
> NR_IRQS_LEGACY by clamping the allocation start to at least that value.
>
> Architectures that do not define NR_IRQS_LEGACY keep the current behaviour
> (effectively 0). Arm/PowerPC/MIPS/LoongArch use legacy IRQ domains for ISA
> interrupts and benefit from this change. x86 and s390 already provide their
> own implementations.
Q: How do all those architectures which do not require the reservation
of the legacy interrupts benefit from that?
A: Not at all
- PowerPC has its own way to deal with that depending on the platform
the kernel runs on as not all platforms require it despite it being
defined.
- ARM only uses it when SPARSE_IRQ=n and does not need it
otherwise. So again this changes behaviour.
- MIPS is only using it for mips/longsoon64 and the rest of MIPS does not
care at all.
So if you need that on loonson, implement arch_dynirq_lower_bound()
instead of making uniformed claims.
Thanks,
tglx
next prev parent reply other threads:[~2026-02-11 11:51 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-11 9:44 [PATCH v2 0/7] Add support for LS7A LPC IRQ for MIPS Loongson systems Icenowy Zheng
2026-02-11 9:44 ` [PATCH v2 1/7] genirq: reserve NR_IRQS_LEGACY IRQs in dynirq by default Icenowy Zheng
2026-02-11 11:51 ` Thomas Gleixner [this message]
2026-02-11 9:44 ` [PATCH v2 2/7] dt-bindings: interrupt-controller: add LS7A PCH LPC Icenowy Zheng
2026-02-11 22:08 ` Rob Herring (Arm)
2026-02-11 9:44 ` [PATCH v2 3/7] irqchip/loongson-pch-lpc: extract non-ACPI-related code from ACPI init Icenowy Zheng
2026-02-11 9:44 ` [PATCH v2 4/7] irqchip/loongson-pch-lpc: add OF init code Icenowy Zheng
2026-02-11 9:44 ` [PATCH v2 5/7] irqchip/loongson-pch-lpc: enable building on MIPS Loongson64 Icenowy Zheng
2026-02-11 9:44 ` [PATCH v2 6/7] MIPS: Loongson64: dts: sort nodes Icenowy Zheng
2026-02-11 9:44 ` [PATCH v2 7/7] MIPS: Loongson64: dts: add node for LS7A PCH LPC Icenowy Zheng
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