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Fri, 10 Jan 2025 08:55:33 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c95b09b2sm184706966b.146.2025.01.10.08.55.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jan 2025 08:55:32 -0800 (PST) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 80D445F8C8; Fri, 10 Jan 2025 16:55:31 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Peter Maydell Cc: David Hildenbrand , Stefan Zabka , qemu-devel@nongnu.org, Paolo Bonzini , Peter Xu , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Richard Henderson Subject: Re: [PATCH v2] physmem: allow cpu_memory_rw_debug to write to MMIO devices In-Reply-To: (Peter Maydell's message of "Fri, 10 Jan 2025 15:44:51 +0000") References: <20241220195923.314208-1-git@zabka.it> <44f99f89-edb6-4007-a367-f7f3b9e10b7b@zabka.it> <4aa676ea-331f-4c8b-be1d-208804ede674@redhat.com> User-Agent: mu4e 1.12.8; emacs 29.4 Date: Fri, 10 Jan 2025 16:55:31 +0000 Message-ID: <871pxa4ni4.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Peter Maydell writes: > On Wed, 8 Jan 2025 at 20:10, David Hildenbrand wrote: >> >> On 08.01.25 19:35, Stefan Zabka wrote: >> > On 21/12/2024 15:55, David Hildenbrand wrote: >> > > Let's wait for opinions from others first. >> > >> > >> > states that two weeks is a reasonable amount of time for follow-up. >> > >> > Should I also ping the original patch? I thought pinging the thread >> > would be more appropriate, as it contains relevant information. >> > >> >> I just pushed a compiling version of the attrs.debug approach to: >> >> https://github.com/davidhildenbrand/qemu/tree/debug_access > > I think this approach (having a 'debug' attribute in the MemTxAttrs > seems reasonable. I do note that if we allow this kind of access > to write to MMIO devices then we are also permitting ELF (and other) > image loads to write to MMIO devices where currently we ignore those. > That means there's probably a class of guest images (of dubious > correctness) which will start writing junk (likely zeroes) into > device model registers; we previously would silently ignore any > such bogus ELF sections. > > Q: should we suggest behaviour for device models if they see a > 'debug =3D 1' transaction, e.g. "don't update your internal state > for a debug read if you have clear-on-read or similar kinds of > register fields" ? What do we do for device models that want to know which CPU things are coming from, as per: https://gitlab.com/qemu-project/qemu/-/issues/124 --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro