From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37BF2E77194 for ; Mon, 30 Dec 2024 10:31:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:References :In-Reply-To:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TLrjSbcEFQaTrgeLz6iDeg2sol347ZcjwwcJKHgFqF0=; b=35yntIB95NttRb 7mqKeOX86/rl2cquXxmZK9gKtnT97EEHRjhA+BD2dgTeqJxhsUUtFaWjx9Ox+c+BOBKelc/vjcAqA FEz6X032U9Qvmozkiskt47iBbV3MDm+1cUA1bceyeuJhNfrksdJoxLldsXsQcwbJh3wTm16+r4U1s BH4MBO2a8GgN3PjlVLzY42G97T6c7TYp5esW6TFt+AQ5dMIqjl1nKHPRoiUtCQTZR5pkkeOrnvdEX Uhffichp7JmJlDTUkBcDcFR+Bq0NRsGmcyuYRpD+hbvFDAojSNW97XLTrkEBCn5EZVxQ3t1b+B6KL oVapkHskMRY440m99T9A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tSD3h-000000052wo-31uQ; Mon, 30 Dec 2024 10:31:37 +0000 Received: from relay4-d.mail.gandi.net ([217.70.183.196]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tSD3f-000000052w5-2Fzb for linux-mtd@lists.infradead.org; Mon, 30 Dec 2024 10:31:37 +0000 Received: by mail.gandi.net (Postfix) with ESMTPSA id D02ACE0002; Mon, 30 Dec 2024 10:31:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1735554692; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ah9Nj1CsYLNqN+ym7Tfi29xnWBTykrM7Cm3xmSOkh3w=; b=b412niyUS2m2riUSohMvVYDBc8Il3FJInCdCH9Nt7a4VN1b/GjNf1EXz/Pzyfc54m6H5a9 MWE/GCVzAugKULqbbrGNTCxaBLtdMx/GMR7iVrE/PqNeG2lB3f/G+TEUzp651oDnh/Wk+f TpKcNu10k0+EcCcrx/V08Pg0LOzSc4NUT54Na5Uoo0IBtF/4CX0B8FH0YdYWrqenS0VEJr l5lDkSPNsrYoE6dOoTmTM++LQ0FLR9feYLqHnhvMmDajqkXiXNb9j94qIhXdGxL3pSb8I+ luqauDjlRtvcTse7Tu1QjkV+vqb/fRiD7UJehxIlJuXaSgXrbmd0rRIbYgrX3Q== From: Miquel Raynal To: Pratyush Yadav Cc: Tudor Ambarus , Michael Walle , Richard Weinberger , Vignesh Raghavendra , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] mtd: spi-nor: winbond: Add support for w25q01jv In-Reply-To: (Pratyush Yadav's message of "Tue, 24 Dec 2024 21:15:41 +0000") References: <20241224-winbond-6-12-rc1-nor-volatile-bit-v1-0-f7c4dff66182@bootlin.com> <20241224-winbond-6-12-rc1-nor-volatile-bit-v1-1-f7c4dff66182@bootlin.com> User-Agent: mu4e 1.12.7; emacs 29.4 Date: Mon, 30 Dec 2024 11:31:31 +0100 Message-ID: <871pxp798c.fsf@bootlin.com> MIME-Version: 1.0 X-GND-Sasl: miquel.raynal@bootlin.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241230_023135_842603_50FA6457 X-CRM114-Status: GOOD ( 62.81 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org SGVsbG8gUHJhdHl1c2gsCgpPbiAyNC8xMi8yMDI0IGF0IDIxOjE1OjQxIEdNVCwgUHJhdHl1c2gg WWFkYXYgPHByYXR5dXNoQGtlcm5lbC5vcmc+IHdyb3RlOgoKPiBPbiBUdWUsIERlYyAyNCAyMDI0 LCBNaXF1ZWwgUmF5bmFsIHdyb3RlOgo+Cj4+IEFkZCBzdXBwb3J0IGZvciBXaW5ib25kIHcyNXEw MWp2IHNwaS1ub3IgY2hpcC4KPj4KPj4gVGhpcyBjaGlwIGlzIGludGVybmFsbHkgbWFkZSBvZiB0 d28gZGllcyB3aXRoIGxpbmVhciBhZGRyZXNzaW5nCj4+IGNhcGFiaWxpdGllcyB0byBtYWtlIGl0 IHRyYW5zcGFyZW50IHRvIHRoZSB1c2VyIHRoYXQgdHdvIGRpZXMgd2VyZQo+PiB1c2VkLiBUaGVy ZSBpcyBvbmUgZHJhd2JhY2sgaG93ZXZlciwgdGhlIHJlYWQgc3RhdHVzIG9wZXJhdGlvbiBpcyBy YWN5Cj4+IGFzIHRoZSBzdGF0dXMgYml0IG9ubHkgZ2l2ZXMgdGhlIGFjdGl2ZSBkaWUgc3RhdHVz IGFuZCBub3QgdGhlIHN0YXR1cyBvZgo+PiB0aGUgb3RoZXIgZGllLiBGb3IgY29tbWFuZHMgYWZm ZWN0aW5nIHRoZSB0d28gZGllcywgaXQgbWVhbnMgaWYgYW5vdGhlcgo+PiBjb21tYW5kIGlzIHNl bnQgdG9vIGZhc3QgYWZ0ZXIgdGhlIGZpcnN0IGRpZSBoYXMgcmV0dXJuZWQgYSB2YWxpZCBzdGF0 dXMKPj4gKGRldmlhdGlvbiBjYW4gYmUgdXAgdG8gMjAwdXMpLCB0aGUgY2hpcCB3aWxsIGdldCBj b3JydXB0ZWQvaW4gYW4KPj4gdW5zdGFibGUgc3RhdGUuCj4+Cj4+IFRoaXMgY2hpcCBoZW5jZSBy ZXF1aXJlcyBhIGJldHRlciBzdGF0dXMgcmVnaXN0ZXIgcmVhZC4gVGhlcmUgYXJlIHRocmVlCj4+ IHNvbHV0aW9ucyBoZXJlOgo+PiAtIEVpdGhlciB3ZSB3YWl0IGFib3V0IDIwMHVzIGFmdGVyIGdl dHRpbmcgYSBmaXJzdCBzdGF0dXMgcmVhZHkKPj4gZmVlZGJhY2ssIHRvIGNvdmVyIHBvc3NpYmxl IGludGVybmFsIGRldmlhdGlvbnMuCj4+IC0gT3Igd2UgYWx3YXlzIGNoZWNrIGFsbCBpbnRlcm5h bCBkaWVzICh3aGljaCB0YWtlcyBhYm91dCAzMHVzIHBlciBkaWUpLgo+Pgo+PiBUaGlzIHNlY29u ZCBvcHRpb24gYmVpbmcgYWx3YXlzIGZhc3RlciBhbmQgYWxzbyBiZWluZyB0b3RhbGx5IHNhZmUs IHdlCj4+IGltcGxlbWVudCBhIHNwZWNpZmljIGhvb2sgZm9yIHRoZSBzdGF0dXMgcmVnaXN0ZXIg cmVhZC4gZmxhc2hfc3BlZWQKPgo+IE1ha2VzIHNlbnNlLgo+Cj4+IGJlbmNobWFya3Mgc2hvdyBu byBkaWZmZXJlbmNlIHdpdGggdGhpcyBpbXBsZW1lbnRhdGlvbiwgY29tcGFyZWQgdG8gdGhlCj4+ IHJlZ3VsYXIgc3RhdHVzIHJlYWQgY29yZSBmdW5jdGlvbiwgdGhlIGRpZmZlcmVuY2UgYmVpbmcg cGFydCBvZiB0aGUKPj4gbmF0dXJhbCBkZXZpYXRpb24gd2l0aCB0aGlzIGJlbmNobWFyazoKPj4K Pj4gCT4gV2l0aG91dCB0aGUgZml4dXAKPj4gCSQgZmxhc2hfc3BlZWQgL2Rldi9tdGQwIC1jMTAw IC1kCj4+IAllcmFzZWJsb2NrIHdyaXRlIHNwZWVkIGlzIDQ0MiBLaUIvcwo+PiAJZXJhc2VibG9j ayByZWFkIHNwZWVkIGlzIDE2MDYgS2lCL3MKPj4gCXBhZ2Ugd3JpdGUgc3BlZWQgaXMgNDM5IEtp Qi9zCj4+IAlwYWdlIHJlYWQgc3BlZWQgaXMgMTUyMCBLaUIvcwo+PiAJMiBwYWdlIHdyaXRlIHNw ZWVkIGlzIDQ0MSBLaUIvcwo+PiAJMiBwYWdlIHJlYWQgc3BlZWQgaXMgMTU2MiBLaUIvcwo+PiAJ ZXJhc2Ugc3BlZWQgaXMgNjggS2lCL3MKPj4KPj4gCT4gV2l0aCB0aGUgZml4dXAKPj4gCSQgZmxh c2hfc3BlZWQgL2Rldi9tdGQwIC1jMTAwIC1kCj4+IAllcmFzZWJsb2NrIHdyaXRlIHNwZWVkIGlz IDQyOCBLaUIvcwo+PiAJZXJhc2VibG9jayByZWFkIHNwZWVkIGlzIDE2MjYgS2lCL3MKPj4gCXBh Z2Ugd3JpdGUgc3BlZWQgaXMgNDI2IEtpQi9zCj4+IAlwYWdlIHJlYWQgc3BlZWQgaXMgMTUzOCBL aUIvcwo+PiAJMiBwYWdlIHdyaXRlIHNwZWVkIGlzIDQyNiBLaUIvcwo+PiAJMiBwYWdlIHJlYWQg c3BlZWQgaXMgMTU3NCBLaUIvcwo+PiAJZXJhc2Ugc3BlZWQgaXMgNjYgS2lCL3MKPj4KPj4gQXMg dGhlcmUgYXJlIHZlcnkgZmV3IHNpdHVhdGlvbnMgd2hlcmUgdGhpcyBjYW4gYWN0dWFsbHkgaGFw cGVuLCBhCj4+IHN0YXR1cyByZWdpc3RlciB3cml0ZSBiZWluZyB0aGUgbW9zdCBsaWtlbHkgb25l LCBhbm90aGVyIHBvc3NpYmlsaXR5Cj4+IG1pZ2h0IGhhdmUgYmVlbiB0byB1c2Ugdm9sYXRpbGUg d3JpdGVzIGluc3RlYWQgb2Ygbm9uLXZvbGF0aWxlIHdyaXRlcywKPj4gYXMgbW9zdCBvZiB0aGUg ZGV2aWF0aW9uIGNvbWVzIGZyb20gdGhlIGFjdGlvbiBvZiB3cml0aW5nIHRoZSBiaXQuIEJ1dAo+ PiB0aGlzIHdvdWxkIG92ZXJsb29rIG90aGVyIHBvc3NpYmxlIGFjdGlvbnMgd2hlcmUgYm90aCBk aWVzIGNhbiBiZSB1c2VkCj4+IGF0IHRoZSBzYW1lIHRpbWUgbGlrZSBhIGNoaXAgZXJhc2UgKG9y IGFueSBlcmFzZSBvdmVyIHRoZSBkaWUgYm91bmRhcnkKPj4gaW4gZ2VuZXJhbCkuIFRoaXMgbGFz dCBhcHByb2FjaCB3b3VsZCBoYXZlIHRoZSBsZWFzdCBpbXBhY3QgYnV0IGJlY2F1c2UKPj4gaXQg ZG9lcyBub3QgZmVlbCBsaWtlIGl0IGlzIHRvdGFsbHkgc2FmZSB0byB1c2UgYW5kIGJlY2F1c2Ug dGhlIGltcGFjdAo+PiBvZiB0aGUgc2Vjb25kIHNvbHV0aW9uIHByZXNlbnRlZCBhYm92ZSBpcyBh bHNvIG5lZ2xpZ2libGUsIHdlIGtlZXAgdGhpcwo+PiBzZWNvbmQgYXBwcm9hY2ggZm9yIG5vdyAo d2hpY2ggY2FuIGJlIGZ1cnRoZXIgdHVuZWQgbGF0ZXIgaWYgaXQgYXBwZWFycwo+PiB0byBiZSB0 b28gaW1wYWN0aW5nIGluIHRoZSBlbmQpLgo+Cj4gSSBhbSBhIGJpdCBjb25mdXNlZCBieSB0aGlz IHBhcmFncmFwaC4gV2hhdCBkbyB5b3UgbWVhbiBieSAidGhpcyIgaW4KPiB0aGUKCiJ0aGlzIiA9 ICJ0aGUgcmFjZSBjb25kaXRpb24iCgo+IGZpcnN0IHNlbnRlbmNlPyBXaGF0IGRvIHN0YXR1cyBy ZWdpc3RlciB3cml0ZXMgaGF2ZSB0byBkbyB3aXRoIHRoZSByZWFkeQo+IGJpdCBiZWluZyByYWN5 PwoKVGhlIGJ1ZyB0aGF0IGhhcyBiZWVuIGV4cGVyaWVuY2VkIGZvbGxvd2VkIHRoaXMgc2VxdWVu Y2U6Ci0gc2VuZCB0aGUgd3JpdGUgZW5hYmxlIGNvbW1hbmQgKG5vbi12b2xhdGlsZSkKLSB3YWl0 IGZvciB0aGUgcmVhZHkvYnVzeSBiaXQsIGllLiB3YWl0IGZvciB0aGUgV0VMIGJpdCB0byBiZSBz ZXQKICBiZWNhdXNlIGl0IGlzIG5vbi12b2xhdGlsZSB3cml0ZQotIGFjdGl2ZSBkaWUgaXMgcmVh ZHksIChidXQgaWRsZSBkaWUgaXMgbm90ISkKLSBlbnRlciA0LWJ5dGUgYWRkcmVzcyBtb2RlLCBv bmx5IHRoZSBkaWUgdGhhdCBpcyByZWFkeSBwcm9jZXNzZXMgdGhlCiAgY29tbWFuZC4KCldlIG9u bHkgb2JzZXJ2ZWQgdGhlIGlzc3VlIGluIHRoaXMgcGFydGljdWxhciBjYXNlIHdoaWNoIGludm9s dmVzCndyaXRpbmcgdGhlIHN0YXR1cyByZWdpc3RlciwgYmVjYXVzZSBpdCBpcyBvbmUgb2YgdGhl IHZlcnkgZmV3IGNvbW1hbmRzCnRhcmdldGluZyBhbGwgZGllcyBhdCB0aGUgc2FtZSB0aW1lLgoK SSBhc3N1bWUgYW5vdGhlciBzZXF1ZW5jZSB0aGF0IG1pZ2h0IGxlYWQgdG8gYSBzaW1pbGFyIGlz c3VlIG1pZ2h0IGJlIGEKY2hpcCBlcmFzdXJlLCBhcyBhbGwgZGllcyBhcmUgaW52b2x2ZWQgaW4g cGFyYWxsZWwsIGJ1dCBtYXliZSB0aGVyZSBhcmUKb3RoZXIgc2l0dWF0aW9ucyBJIGRpZCBub3Qg dGhpbmsgYWJvdXQgd2hpY2ggbWlnaHQgYmUgcmFjeSBhcyB3ZWxsLgoKPiBJIHdvdWxkIGFzc3Vt ZSB0aG9zZSB3b3VsZCBiZSBuZWFybHkgaW5zdGFudCBzaW5jZQo+IHN0YXR1cyByZWdpc3RlcnMg YXJlIHVzdWFsbHkgdm9sYXRpbGUuIFdoYXQgZG8gdm9sYXRpbGUgd3JpdGVzIG1lYW4gaW4KPiB0 aGlzIGNvbnRleHQ/CgpZb3UgYXJlIGFjdHVhbGx5IHJpZ2h0LiBTdGF0dXMgcmVnaXN0ZXIgYml0 cyBjYW4gYmUgdm9sYXRpbGUgKGluIHRoaXMKY2FzZSB3cml0aW5nIHRoZSBiaXRzIHRoZW1zZWx2 ZXMgaXMgYWxtb3N0IGluc3RhbnQpIGJ1dCBjdXJyZW50bHkgd2hlbgp3ZSBhbGxvdyB0aGlzIHJl Z2lzdGVyIHRvIGJlIHdyaXRhYmxlIGJ5IHNlbmRpbmcgdGhlIHdyaXRlIGVuYWJsZSAoMDZoKQpj b21tYW5kLCB0aGUgbm9uLXZvbGF0aWxlIHdheSBpcyB1c2VkLCBpZS4gdGhlIHN0YXRlIG9mIHRo ZSBiaXQgaXRzZWxmCmlzIHN0b3JlZCBpbiBub24tdm9sYXRpbGUgbWVtb3J5IGFuZCB3cml0ZSBk dXJhdGlvbnMgY2FuIHZhcnkgZnJvbSBvbmUKZGllIHRvIGFub3RoZXIuCgpXaW5ib25kIGNoaXBz IChtYXliZSB0aGlzIGlzIGEgc2hhcmVkIGNhcGFiaWxpdHk/KSBhY2NlcHRzIGFub3RoZXIKY29t bWFuZCwgIldyaXRlIEVuYWJsZSBmb3IgVm9sYXRpbGUgU3RhdHVzIFJlZ2lzdGVyICg1MGgpIiwg d2hpY2gKc3BlY2lmaWNhbGx5IGNoYW5nZSB0aGUgc3RhdHVzIHJlZ2lzdGVyIGJpdHMgdG8gdXNl IHRoZSB2b2xhdGlsZSBtZXRob2QuCgpIZW5jZSwgaWYgdGhlIG9ubHkgc2l0dWF0aW9uIHdlIHdh bnQgdG8gc29sdmUgaXMgdGhlIHN0YXR1cyByZWdpc3RlcgphY2Nlc3MsIHRoZW4gd2UgbWF5IGp1 c3QgZW5hYmxlIHRoaXMgY29tbWFuZCAodGhpcyBpcyB0aGUgdGhpcmQgc29sdXRpb24KSSB0cmll ZCB0byBleHBsYWluIGluIHRoZSBjb21taXQgbG9nKSwgYnV0IGlmIHdlIHRoaW5rIHRoZXJlIGFy ZSBvdGhlcgpyYWN5IHNpdHVhdGlvbnMsIHRoaXMgYXBwcm9hY2ggaXMgbm90IGNvbXBsZXRlIGFu ZCB3ZSBtdXN0IGZhbGxiYWNrIHRvCm9uZSBvZiB0aGUgYXBwcm9hY2hlcyBsaXN0ZWQgYWJvdmUu Cgo+Pgo+PiBIb3dldmVyLCB0aGUgZml4dXAsIHdoYXRldmVyIHdoaWNoIG9uZSB3ZSBwaWNrLCBt dXN0IGJlIGFwcGxpZWQgb24KPj4gbXVsdGktZGllIGNoaXBzLCB3aGljaCBoZW5jZSBtdXN0IGJl IHByb3Blcmx5IGZsYWdnZWQuIFRoZSBTRkRQIHRhYmxlcwo+PiBpbXBsZW1lbnRlZCBnaXZlIGEg bG90IG9mIGluZm9ybWF0aW9uIGJ1dCB0aGUgZGllIGRldGFpbHMgYXJlIHBhcnQgb2YgYW4KPj4g b3B0aW9uYWwgdGFibGUgdGhhdCBpcyBub3QgaW1wbGVtZW50ZWQsIGhlbmNlIHdlIHVzZSBhIHBv c3QgcGFyc2luZwo+PiBmaXh1cCBob29rIHRvIHNldCB0aGUgcGFyYW1zLT5uX2RpY2UgdmFsdWUg bWFudWFsbHkuCj4+Cj4+IExpbms6IGh0dHBzOi8vd3d3LndpbmJvbmQuY29tL3Jlc291cmNlLWZp bGVzL1cyNVEwMUpWJTIwU1BJJTIwUmV2RSUyMDAzMDQyMDI0JTIwUGx1cy5wZGYKPj4gU2lnbmVk LW9mZi1ieTogTWlxdWVsIFJheW5hbCA8bWlxdWVsLnJheW5hbEBib290bGluLmNvbT4KPj4gLS0t Cj4+Cj4+IEhlcmUgaXMgdGhlIGJhc2ljIHRlc3QgcHJvY2VkdXJlIG91dHB1dDoKPj4KPj4gJCBj YXQgL3N5cy9idXMvc3BpL2RldmljZXMvc3BpMC4wL3NwaS1ub3IvcGFydG5hbWUKPj4gdzI1cTAx anYKPj4gJCBjYXQgL3N5cy9idXMvc3BpL2RldmljZXMvc3BpMC4wL3NwaS1ub3IvamVkZWNfaWQK Pj4gZWY0MDIxCj4+ICQgY2F0IC9zeXMvYnVzL3NwaS9kZXZpY2VzL3NwaTAuMC9zcGktbm9yL21h bnVmYWN0dXJlcgo+PiB3aW5ib25kCj4+ICQgeHhkIC1wIC9zeXMvYnVzL3NwaS9kZXZpY2VzL3Nw aTAuMC9zcGktbm9yL3NmZHAKPj4gNTM0NjQ0NTAwNjAxMDFmZjAwMDYwMTEwODAwMDAwZmY4NDAw MDEwMmQwMDAwMGZmMDMwMDAxMDJmMDAwCj4+IDAwZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZm ZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZgo+PiBmZmZmZmZmZmZmZmZmZmZmZmZmZmZm ZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmYKPj4gZmZmZmZmZmZmZmZmZmZm ZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmCj4+IGZmZmZmZmZm ZmZmZmZmZmZlNTIwZmJmZmZmZmZmZjNmNDRlYjA4NmIwODNiNDJiYmZlZmZmZmZmZmZmZgo+PiAw MDAwZmZmZjQwZWIwYzIwMGY1MjEwZDgwMDAwMzYwMmE2MDA4MmVhMTRlMmU5NjM3NjMzN2E3NTdh NzUKPj4gZjdhMmQ1NWMxOWY3NGRmZmU5NzBmOWE1ZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZmZm ZmZmZmZmZjBhCj4+IGYwZmYyMWZmZGNmZgo+PiAkIG1kNXN1bSAvc3lzL2J1cy9zcGkvZGV2aWNl cy9zcGkwLjAvc3BpLW5vci9zZmRwCj4+IGE3YjlkYmY3NmU5OWEzM2RiOTllNTU3YjY2NzY1ODhh ICAvc3lzL2J1cy9zcGkvZGV2aWNlcy9zcGkwLjAvc3BpLW5vci9zZmRwCj4+ICQgZGQgaWY9L2Rl di91cmFuZG9tIG9mPS4vcXNwaV90ZXN0IGJzPTFNIGNvdW50PTEKPj4gMSswIHJlY29yZHMgaW4K Pj4gMSswIHJlY29yZHMgb3V0Cj4+ICQgbXRkX2RlYnVnIHdyaXRlIC9kZXYvbXRkMCAwIDEwNDg1 NzYgcXNwaV90ZXN0Cj4+IENvcGllZCAxMDQ4NTc2IGJ5dGVzIGZyb20gcXNwaV90ZXN0IHRvIGFk ZHJlc3MgMHgwMDAwMDAwMCBpbiBmbGFzaAo+PiAkIG10ZF9kZWJ1ZyBlcmFzZSAvZGV2L210ZDAg MCAxMDQ4NTc2Cj4+IEVyYXNlZCAxMDQ4NTc2IGJ5dGVzIGZyb20gYWRkcmVzcyAweDAwMDAwMDAw IGluIGZsYXNoCj4+ICQgbXRkX2RlYnVnIHJlYWQgL2Rldi9tdGQwIDAgMTA0ODU3NiBxc3BpX3Jl YWQKPj4gQ29waWVkIDEwNDg1NzYgYnl0ZXMgZnJvbSBhZGRyZXNzIDB4MDAwMDAwMDAgaW4gZmxh c2ggdG8gcXNwaV9yZWFkCj4+ICQgaGV4ZHVtcCBxc3BpX3JlYWQKPj4gMDAwMDAwMCBmZmZmIGZm ZmYgZmZmZiBmZmZmIGZmZmYgZmZmZiBmZmZmIGZmZmYKPj4gKgo+PiAwMTAwMDAwCj4+ICQgbXRk X2RlYnVnIHdyaXRlIC9kZXYvbXRkMCAwIDEwNDg1NzYgcXNwaV90ZXN0Cj4+IENvcGllZCAxMDQ4 NTc2IGJ5dGVzIGZyb20gcXNwaV90ZXN0IHRvIGFkZHJlc3MgMHgwMDAwMDAwMCBpbiBmbGFzaAo+ PiAkIG10ZF9kZWJ1ZyByZWFkIC9kZXYvbXRkMCAwIDEwNDg1NzYgcXNwaV9yZWFkCj4+IENvcGll ZCAxMDQ4NTc2IGJ5dGVzIGZyb20gYWRkcmVzcyAweDAwMDAwMDAwIGluIGZsYXNoIHRvIHFzcGlf cmVhZAo+PiAkIHNoYTFzdW0gcXNwaV90ZXN0IHFzcGlfcmVhZAo+PiBiZWNmMzA5N2MwYmJmZjBk ZDZmMjA0ZmZlNWJmNTc1ZTZjNDNmNzkyICBxc3BpX3Rlc3QKPj4gYmVjZjMwOTdjMGJiZmYwZGQ2 ZjIwNGZmZTViZjU3NWU2YzQzZjc5MiAgcXNwaV9yZWFkCj4+IC0tLQo+PiAgZHJpdmVycy9tdGQv c3BpLW5vci93aW5ib25kLmMgfCA4MiArKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysr KysrKysrKysrCj4+ICAxIGZpbGUgY2hhbmdlZCwgODIgaW5zZXJ0aW9ucygrKQo+Pgo+PiBkaWZm IC0tZ2l0IGEvZHJpdmVycy9tdGQvc3BpLW5vci93aW5ib25kLmMgYi9kcml2ZXJzL210ZC9zcGkt bm9yL3dpbmJvbmQuYwo+PiBpbmRleCA4ZDBhMDBkNjllMTIzMzk4ODg3NmExNTQ3OWQ3M2M1ZmU4 OTljNTQyLi40NjkxZTdhMjdiYTFkNzBjNzU5MzJjNGU2YjYwZmUzNjEwMjEzOGJlIDEwMDY0NAo+ PiAtLS0gYS9kcml2ZXJzL210ZC9zcGktbm9yL3dpbmJvbmQuYwo+PiArKysgYi9kcml2ZXJzL210 ZC9zcGktbm9yL3dpbmJvbmQuYwo+PiBAQCAtMTAsNiArMTAsNyBAQAo+PiAgCj4+ICAjZGVmaW5l IFdJTkJPTkRfTk9SX09QX1JERUFSCTB4YzgJLyogUmVhZCBFeHRlbmRlZCBBZGRyZXNzIFJlZ2lz dGVyICovCj4+ICAjZGVmaW5lIFdJTkJPTkRfTk9SX09QX1dSRUFSCTB4YzUJLyogV3JpdGUgRXh0 ZW5kZWQgQWRkcmVzcyBSZWdpc3RlciAqLwo+PiArI2RlZmluZSBXSU5CT05EX05PUl9PUF9TRUxE SUUJMHhjMgkvKiBTZWxlY3QgYWN0aXZlIGRpZSAqLwo+PiAgCj4+ICAjZGVmaW5lIFdJTkJPTkRf Tk9SX1dSRUFSX09QKGJ1ZikJCQkJCVwKPj4gIAlTUElfTUVNX09QKFNQSV9NRU1fT1BfQ01EKFdJ TkJPTkRfTk9SX09QX1dSRUFSLCAwKSwJCVwKPj4gQEAgLTE3LDYgKzE4LDEyIEBACj4+ICAJCSAg IFNQSV9NRU1fT1BfTk9fRFVNTVksCQkJCQlcCj4+ICAJCSAgIFNQSV9NRU1fT1BfREFUQV9PVVQo MSwgYnVmLCAwKSkKPj4gIAo+PiArI2RlZmluZSBXSU5CT05EX05PUl9TRUxESUVfT1AoYnVmKQkJ CQkJXAo+PiArCVNQSV9NRU1fT1AoU1BJX01FTV9PUF9DTUQoV0lOQk9ORF9OT1JfT1BfU0VMRElF LCAwKSwJCVwKPj4gKwkJICAgU1BJX01FTV9PUF9OT19BRERSLAkJCQkJXAo+PiArCQkgICBTUElf TUVNX09QX05PX0RVTU1ZLAkJCQkJXAo+PiArCQkgICBTUElfTUVNX09QX0RBVEFfT1VUKDEsIGJ1 ZiwgMCkpCj4+ICsKPj4gIHN0YXRpYyBpbnQKPj4gIHcyNXExMjhfcG9zdF9iZnB0X2ZpeHVwcyhz dHJ1Y3Qgc3BpX25vciAqbm9yLAo+PiAgCQkJIGNvbnN0IHN0cnVjdCBzZmRwX3BhcmFtZXRlcl9o ZWFkZXIgKmJmcHRfaGVhZGVyLAo+PiBAQCAtNjYsNiArNzMsMjYgQEAgc3RhdGljIGNvbnN0IHN0 cnVjdCBzcGlfbm9yX2ZpeHVwcyB3MjVxMjU2X2ZpeHVwcyA9IHsKPj4gIAkucG9zdF9iZnB0ID0g dzI1cTI1Nl9wb3N0X2JmcHRfZml4dXBzLAo+PiAgfTsKPj4gIAo+PiArc3RhdGljIGludAo+PiAr dzI1cTB4anZfcG9zdF9iZnB0X2ZpeHVwcyhzdHJ1Y3Qgc3BpX25vciAqbm9yLAo+PiArCQkJICBj b25zdCBzdHJ1Y3Qgc2ZkcF9wYXJhbWV0ZXJfaGVhZGVyICpiZnB0X2hlYWRlciwKPj4gKwkJCSAg Y29uc3Qgc3RydWN0IHNmZHBfYmZwdCAqYmZwdCkKPj4gK3sKPj4gKwkvKgo+PiArCSAqIFNGRFAg c3VwcG9ydHMgZGljZSBudW1iZXJzLCBidXQgdGhpcyBpbmZvcm1hdGlvbiBpcyBvbmx5IGF2YWls YWJsZSBpbgo+PiArCSAqIG9wdGlvbmFsIGFkZGl0aW9uYWwgdGFibGVzIHdoaWNoIGFyZSBub3Qg cHJvdmlkZWQgYnkgdGhlc2UgY2hpcHMuCj4+ICsJICogRGljZSBudW1iZXIgaGFzIGFuIGltcGFj dCB0aG91Z2gsIGJlY2F1c2UgdGhlc2UgZGV2aWNlcyBuZWVkIGV4dHJhCj4+ICsJICogY2FyZSB3 aGVuIHJlYWRpbmcgdGhlIGJ1c3kgYml0Lgo+PiArCSAqLwo+PiArCW5vci0+cGFyYW1zLT5uX2Rp Y2UgPSBub3ItPnBhcmFtcy0+c2l6ZSAvIFNaXzY0TTsKPgo+IG5fZGljZSBpcyBzZXQgYnkgc3Bp X25vcl9wYXJzZV9zY2NyX21jKCksIHdoaWNoIHJ1bnMgX2FmdGVyXyBwb3N0LUJGUFQKPiBmaXh1 cHMuIFRoaXMgZG9lc24ndCBtYXR0ZXIgaW4gcHJhY3RpY2Ugc2luY2UgeW91IHNheSB0aGF0IHRo ZSBjaGlwCj4gZG9lc24ndCBoYXZlIGEgU0NDUl9NQyB0YWJsZSBidXQgSSB0aGluayBpdCBzdGls bCBpcyBhIGdvb2QgaWRlYSB0bwo+IGZvbGxvdyB0aGUgaW5pdGlhbGl6YXRpb24gb3JkZXIgYW5k IGRvIHRoaXMgaW4gdGhlIHBvc3QtU0ZEUCBob29rLgoKSSBtdXN0IGhhdmUgYmVlbiBtaXNsZWFk IGJ5IHRoZSBuYW1lcywgaW5kZWVkLCBJJ2xsIGNoZWNrLgoKPgo+PiArCj4+ICsJcmV0dXJuIDA7 Cj4+ICt9Cj4+ICsKPj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3Qgc3BpX25vcl9maXh1cHMgdzI1cTB4 anZfZml4dXBzID0gewo+PiArCS5wb3N0X2JmcHQgPSB3MjVxMHhqdl9wb3N0X2JmcHRfZml4dXBz LAo+PiArfTsKPj4gKwo+PiAgc3RhdGljIGNvbnN0IHN0cnVjdCBmbGFzaF9pbmZvIHdpbmJvbmRf bm9yX3BhcnRzW10gPSB7Cj4+ICAJewo+PiAgCQkuaWQgPSBTTk9SX0lEKDB4ZWYsIDB4MzAsIDB4 MTApLAo+PiBAQCAtMTQ2LDYgKzE3MywxMSBAQCBzdGF0aWMgY29uc3Qgc3RydWN0IGZsYXNoX2lu Zm8gd2luYm9uZF9ub3JfcGFydHNbXSA9IHsKPj4gIAkJLm5hbWUgPSAidzI1cTUxMmp2cSIsCj4+ ICAJCS5zaXplID0gU1pfNjRNLAo+PiAgCQkubm9fc2ZkcF9mbGFncyA9IFNFQ1RfNEsgfCBTUElf Tk9SX0RVQUxfUkVBRCB8IFNQSV9OT1JfUVVBRF9SRUFELAo+PiArCX0sIHsKPj4gKwkJLmlkID0g U05PUl9JRCgweGVmLCAweDQwLCAweDIxKSwKPj4gKwkJLm5hbWUgPSAidzI1cTAxanYiLAo+Cj4g V2Ugbm8gbG9uZ2VyIHNldCB0aGUgbmFtZSBmb3IgbmV3IGZsYXNoIGVudHJpZXMuIEJ1dCBrbm93 aW5nIHRoZSBmbGFzaAo+IG5hbWUgZm9yIGFuIGVudHJ5IGlzIHN0aWxsIHVzZWZ1bCwgc28gbWFr ZSB0aGlzIGEgY29tbWVudCBvbiB0b3Agb2YgdGhlCj4gZW50cnkuCgpBY3R1YWxseSB3aXRob3V0 IHRoZSBmbGFzaCBlbnRyeSB0aGUgZml4dXBzIGNhbm5vdCBhcHBseSwgc28gSSdkIGV4cGVjdAph bnkgZmxhc2ggd2l0aCBmaXh1cHMgKGxpa2UgdGhpcyBvbmUpIHRvIGJlIGxpc3RlZCBhdCBsZWFz dD8gU2FpZApvdGhlcndpc2UsIHdoYXQgY29tbWVudCB3b3VsZCB5b3UgZXhwZWN0IGhlcmU/Cgo+ Cj4+ICsJCS5ub19zZmRwX2ZsYWdzID0gU0VDVF80SyB8IFNQSV9OT1JfRFVBTF9SRUFEIHwgU1BJ X05PUl9RVUFEX1JFQUQsCj4KPiBTaW5jZSB0aGUgZmxhc2ggaGFzIGFuIFNGRFAgdGFibGUsIHlv dSBwcm9iYWJseSBkb24ndCBuZWVkIHRoZXNlIGZsYWdzLgo+IENhbiB5b3UgdHJ5IHJlbW92aW5n IHRoaXMgbGluZSBhbmQgc2VlIGlmIHRoaW5ncyBzdGlsbCB3b3JrIGZpbmU/CgpHYXNwLiBTZWNv bmQgdGltZSBJIGZvcmdldCB0byByZW1vdmUgdGhlc2UuIFllcywgdGhpcyBpcyBhIGNvcHktcGFz dGUKbGVmdC1vdmVyIHdoaWNoIGlzIG5vdCBuZWVkZWQuIEknbGwgZG91YmxlIGNoZWNrIGl0IGlz IGFjdHVhbGx5IG5vdApuZWVkZWQgdGhvdWdoLgoKPgo+PiArCQkuZml4dXBzID0gJncyNXEweGp2 X2ZpeHVwcywKPj4gIAl9LCB7Cj4+ICAJCS5pZCA9IFNOT1JfSUQoMHhlZiwgMHg1MCwgMHgxMiks Cj4+ICAJCS5uYW1lID0gIncyNXEyMGJ3IiwKPj4gQEAgLTI4OSw2ICszMjEsMzcgQEAgc3RhdGlj IGludCB3aW5ib25kX25vcl93cml0ZV9lYXIoc3RydWN0IHNwaV9ub3IgKm5vciwgdTggZWFyKQo+ PiAgCXJldHVybiByZXQ7Cj4+ICB9Cj4+ICAKPj4gKy8qKgo+PiArICogd2luYm9uZF9ub3Jfc2Vs ZWN0X2RpZSgpIC0gU2V0IGFjdGl2ZSBkaWUuCj4+ICsgKiBAbm9yOglwb2ludGVyIHRvICdzdHJ1 Y3Qgc3BpX25vcicuCj4+ICsgKiBAZGllOglkaWUgdG8gc2V0IGFjdGl2ZS4KPj4gKyAqCj4+ICsg KiBSZXR1cm46IDAgb24gc3VjY2VzcywgLWVycm5vIG90aGVyd2lzZS4KPj4gKyAqLwo+PiArc3Rh dGljIGludCB3aW5ib25kX25vcl9zZWxlY3RfZGllKHN0cnVjdCBzcGlfbm9yICpub3IsIHU4IGRp ZSkKPj4gK3sKPj4gKwlpbnQgcmV0Owo+PiArCj4+ICsJbm9yLT5ib3VuY2VidWZbMF0gPSBkaWU7 Cj4+ICsKPj4gKwlpZiAobm9yLT5zcGltZW0pIHsKPj4gKwkJc3RydWN0IHNwaV9tZW1fb3Agb3Ag PSBXSU5CT05EX05PUl9TRUxESUVfT1Aobm9yLT5ib3VuY2VidWYpOwo+PiArCj4+ICsJCXNwaV9u b3Jfc3BpbWVtX3NldHVwX29wKG5vciwgJm9wLCBub3ItPnJlZ19wcm90byk7Cj4+ICsKPj4gKwkJ cmV0ID0gc3BpX21lbV9leGVjX29wKG5vci0+c3BpbWVtLCAmb3ApOwo+PiArCX0gZWxzZSB7Cj4+ ICsJCXJldCA9IHNwaV9ub3JfY29udHJvbGxlcl9vcHNfd3JpdGVfcmVnKG5vciwKPj4gKwkJCQkJ CSAgICAgICBXSU5CT05EX05PUl9PUF9TRUxESUUsCj4+ICsJCQkJCQkgICAgICAgbm9yLT5ib3Vu Y2VidWYsIDEpOwo+PiArCX0KPj4gKwo+PiArCWlmIChyZXQpCj4+ICsJCWRldl9kYmcobm9yLT5k ZXYsICJlcnJvciAlZCBzZWxlY3RpbmcgZGllICVkXG4iLCByZXQsIGRpZSk7Cj4+ICsKPj4gKwly ZXR1cm4gcmV0Owo+PiArfQo+PiArCj4+ICAvKioKPj4gICAqIHdpbmJvbmRfbm9yX3NldF80Ynl0 ZV9hZGRyX21vZGUoKSAtIFNldCA0LWJ5dGUgYWRkcmVzcyBtb2RlIGZvciBXaW5ib25kCj4+ICAg KiBmbGFzaGVzLgo+PiBAQCAtMzIyLDYgKzM4NSwyMiBAQCBzdGF0aWMgaW50IHdpbmJvbmRfbm9y X3NldF80Ynl0ZV9hZGRyX21vZGUoc3RydWN0IHNwaV9ub3IgKm5vciwgYm9vbCBlbmFibGUpCj4+ ICAJcmV0dXJuIHNwaV9ub3Jfd3JpdGVfZGlzYWJsZShub3IpOwo+PiAgfQo+PiAgCj4KPiBBZGRp bmcgYSBzaG9ydCBjb21tZW50IGFib3V0IHdoeSB0aGlzIGlzIG5lZWRlZCB3b3VsZCBiZSBuaWNl LCBhbmQKPiByZWFkZXJzIHdvbid0IGFsd2F5cyBoYXZlIHRvIGRvIGEgZ2l0IGJsYW1lIHRvIGZp bmQgb3V0LgoKU3VyZS4KCj4KPj4gK3N0YXRpYyBpbnQgd2luYm9uZF9tdWx0aV9kaWVfcmVhZHko c3RydWN0IHNwaV9ub3IgKm5vcikKPj4gK3sKPj4gKwlpbnQgcmV0LCBpOwo+PiArCj4+ICsJZm9y IChpID0gMDsgaSA8IG5vci0+cGFyYW1zLT5uX2RpY2U7IGkrKykgewo+PiArCQlyZXQgPSB3aW5i b25kX25vcl9zZWxlY3RfZGllKG5vciwgaSk7Cj4+ICsJCWlmIChyZXQpCj4+ICsJCQlyZXR1cm4g cmV0Owo+PiArCj4+ICsJCWlmICghc3BpX25vcl9zcl9yZWFkeShub3IpKQo+Cj4gc3BpX25vcl9z cl9yZWFkeSgpIGNhbiBhbHNvIHJldHVybiAtZXJybm8sIHdoaWNoIHdvdWxkIGJlIHRyZWF0ZWQg aGVyZQo+IGFzIGJlaW5nIHJlYWR5LCB3aGljaCBvYnZpb3VzbHkgaXNuJ3QgcmlnaHQuIFRoaXMg c2hvdWxkIGFsc28gY2hlY2sgZm9yCj4gYSByZXR1cm4gdmFsdWUgPCAwLgoKVGhhdCdzIHRydWUu Cgo+Cj4+ICsJCQlyZXR1cm4gMDsKPj4gKwl9Cj4+ICsKPj4gKwlyZXR1cm4gMTsKPj4gK30KPj4g Kwo+PiAgc3RhdGljIGNvbnN0IHN0cnVjdCBzcGlfbm9yX290cF9vcHMgd2luYm9uZF9ub3Jfb3Rw X29wcyA9IHsKPj4gIAkucmVhZCA9IHNwaV9ub3Jfb3RwX3JlYWRfc2VjciwKPj4gIAkud3JpdGUg PSBzcGlfbm9yX290cF93cml0ZV9zZWNyLAo+PiBAQCAtMzM0LDYgKzQxMyw5IEBAIHN0YXRpYyBp bnQgd2luYm9uZF9ub3JfbGF0ZV9pbml0KHN0cnVjdCBzcGlfbm9yICpub3IpCj4+ICB7Cj4+ICAJ c3RydWN0IHNwaV9ub3JfZmxhc2hfcGFyYW1ldGVyICpwYXJhbXMgPSBub3ItPnBhcmFtczsKPj4g IAo+PiArCWlmIChwYXJhbXMtPm5fZGljZSA+IDEpCj4+ICsJCXBhcmFtcy0+cmVhZHkgPSB3aW5i b25kX211bHRpX2RpZV9yZWFkeTsKPj4gKwo+Cj4gSXMgdGhpcyB0cnVlIGZvciBhbGwgbXVsdGkt ZGllIFdpbmJvbmQgZmxhc2hlcywgYW5kIGdvaW5nIHRvIGhvbGQgdHJ1ZQo+IGZvciBmdXR1cmUg b25lcz8gSWYgbm90LCBJIHN1cHBvc2UgdGhpcyBzaG91bGQgZ28gaW4gdGhlIGZsYXNoLXNwZWNp ZmljCj4gZml4dXAgaG9vay4gRG8gaXQgaW4gZWl0aGVyIHRoZSBmbGFzaC1zcGVjaWZpYyBsYXRl X2luaXQgaG9vaywgb3IgaW4gdGhlCj4gcG9zdF9zZmRwIGhvb2ssIEkgaGF2ZSBubyBzdHJvbmcg b3BpbmlvbnMuCgpUaGlzIGlzIGFuIGluZm9ybWF0aW9uIGhhcmQgdG8gZ2F0aGVyLCBJIGFzc3Vt ZWQgaXQgd2FzIGFsd2F5cyBsaWtlIHRoYXQKd2l0aCBXaW5ib25kIGZsYXNoZXMsIEknbGwgdHJ5 IHRvIGZpbmQgbW9yZSBhYm91dCBpdC4KClRoYW5rcyBmb3IgdGhlIHJldmlldyEKTWlxdcOobAoK X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkxp bnV4IE1URCBkaXNjdXNzaW9uIG1haWxpbmcgbGlzdApodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9y Zy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LW10ZC8K From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 940FD139D19 for ; Mon, 30 Dec 2024 10:31:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.196 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735554697; cv=none; b=EfyL3M/CNiixJ16ZdqETG+D5i0ie6kh9ZOo0zNi1jslrfUOfr+e6fkQoQ1PTX57RLlBRu4GkM0m67mpaHKyVjgxdL2w6rGw4zcGsCq7dgcvPH0wyoTx0IpfJaZEUcTfkjDvmj9g7V8NQD8ZA80hVWopqBH38YVu0SfPMd3rTSWw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735554697; c=relaxed/simple; bh=W5ll/iXG/ZiqQwL4tIiWcW3LOfG/KLVe4Vnu4TmSE2I=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=QFoDPw8UHicahSAAVZcaQd0axIo2DQjPPhr7hqujdocM5JInWzEA2zTDxJyN+RN0R8M+AzleImb6NOId/EmgUuVsCXEzzdqxWvXPoe0tNJ+Ge5xCXZkGqxdsf1ekZbUSCUpWPPesuovsmsJqwHgAGHpOXI2D+a+l27AjrOwaVs0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=b412niyU; arc=none smtp.client-ip=217.70.183.196 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="b412niyU" Received: by mail.gandi.net (Postfix) with ESMTPSA id D02ACE0002; Mon, 30 Dec 2024 10:31:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1735554692; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ah9Nj1CsYLNqN+ym7Tfi29xnWBTykrM7Cm3xmSOkh3w=; b=b412niyUS2m2riUSohMvVYDBc8Il3FJInCdCH9Nt7a4VN1b/GjNf1EXz/Pzyfc54m6H5a9 MWE/GCVzAugKULqbbrGNTCxaBLtdMx/GMR7iVrE/PqNeG2lB3f/G+TEUzp651oDnh/Wk+f TpKcNu10k0+EcCcrx/V08Pg0LOzSc4NUT54Na5Uoo0IBtF/4CX0B8FH0YdYWrqenS0VEJr l5lDkSPNsrYoE6dOoTmTM++LQ0FLR9feYLqHnhvMmDajqkXiXNb9j94qIhXdGxL3pSb8I+ luqauDjlRtvcTse7Tu1QjkV+vqb/fRiD7UJehxIlJuXaSgXrbmd0rRIbYgrX3Q== From: Miquel Raynal To: Pratyush Yadav Cc: Tudor Ambarus , Michael Walle , Richard Weinberger , Vignesh Raghavendra , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] mtd: spi-nor: winbond: Add support for w25q01jv In-Reply-To: (Pratyush Yadav's message of "Tue, 24 Dec 2024 21:15:41 +0000") References: <20241224-winbond-6-12-rc1-nor-volatile-bit-v1-0-f7c4dff66182@bootlin.com> <20241224-winbond-6-12-rc1-nor-volatile-bit-v1-1-f7c4dff66182@bootlin.com> User-Agent: mu4e 1.12.7; emacs 29.4 Date: Mon, 30 Dec 2024 11:31:31 +0100 Message-ID: <871pxp798c.fsf@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: miquel.raynal@bootlin.com Hello Pratyush, On 24/12/2024 at 21:15:41 GMT, Pratyush Yadav wrote: > On Tue, Dec 24 2024, Miquel Raynal wrote: > >> Add support for Winbond w25q01jv spi-nor chip. >> >> This chip is internally made of two dies with linear addressing >> capabilities to make it transparent to the user that two dies were >> used. There is one drawback however, the read status operation is racy >> as the status bit only gives the active die status and not the status of >> the other die. For commands affecting the two dies, it means if another >> command is sent too fast after the first die has returned a valid status >> (deviation can be up to 200us), the chip will get corrupted/in an >> unstable state. >> >> This chip hence requires a better status register read. There are three >> solutions here: >> - Either we wait about 200us after getting a first status ready >> feedback, to cover possible internal deviations. >> - Or we always check all internal dies (which takes about 30us per die). >> >> This second option being always faster and also being totally safe, we >> implement a specific hook for the status register read. flash_speed > > Makes sense. > >> benchmarks show no difference with this implementation, compared to the >> regular status read core function, the difference being part of the >> natural deviation with this benchmark: >> >> > Without the fixup >> $ flash_speed /dev/mtd0 -c100 -d >> eraseblock write speed is 442 KiB/s >> eraseblock read speed is 1606 KiB/s >> page write speed is 439 KiB/s >> page read speed is 1520 KiB/s >> 2 page write speed is 441 KiB/s >> 2 page read speed is 1562 KiB/s >> erase speed is 68 KiB/s >> >> > With the fixup >> $ flash_speed /dev/mtd0 -c100 -d >> eraseblock write speed is 428 KiB/s >> eraseblock read speed is 1626 KiB/s >> page write speed is 426 KiB/s >> page read speed is 1538 KiB/s >> 2 page write speed is 426 KiB/s >> 2 page read speed is 1574 KiB/s >> erase speed is 66 KiB/s >> >> As there are very few situations where this can actually happen, a >> status register write being the most likely one, another possibility >> might have been to use volatile writes instead of non-volatile writes, >> as most of the deviation comes from the action of writing the bit. But >> this would overlook other possible actions where both dies can be used >> at the same time like a chip erase (or any erase over the die boundary >> in general). This last approach would have the least impact but because >> it does not feel like it is totally safe to use and because the impact >> of the second solution presented above is also negligible, we keep this >> second approach for now (which can be further tuned later if it appears >> to be too impacting in the end). > > I am a bit confused by this paragraph. What do you mean by "this" in > the "this" =3D "the race condition" > first sentence? What do status register writes have to do with the ready > bit being racy? The bug that has been experienced followed this sequence: - send the write enable command (non-volatile) - wait for the ready/busy bit, ie. wait for the WEL bit to be set because it is non-volatile write - active die is ready, (but idle die is not!) - enter 4-byte address mode, only the die that is ready processes the command. We only observed the issue in this particular case which involves writing the status register, because it is one of the very few commands targeting all dies at the same time. I assume another sequence that might lead to a similar issue might be a chip erasure, as all dies are involved in parallel, but maybe there are other situations I did not think about which might be racy as well. > I would assume those would be nearly instant since > status registers are usually volatile. What do volatile writes mean in > this context? You are actually right. Status register bits can be volatile (in this case writing the bits themselves is almost instant) but currently when we allow this register to be writable by sending the write enable (06h) command, the non-volatile way is used, ie. the state of the bit itself is stored in non-volatile memory and write durations can vary from one die to another. Winbond chips (maybe this is a shared capability?) accepts another command, "Write Enable for Volatile Status Register (50h)", which specifically change the status register bits to use the volatile method. Hence, if the only situation we want to solve is the status register access, then we may just enable this command (this is the third solution I tried to explain in the commit log), but if we think there are other racy situations, this approach is not complete and we must fallback to one of the approaches listed above. >> >> However, the fixup, whatever which one we pick, must be applied on >> multi-die chips, which hence must be properly flagged. The SFDP tables >> implemented give a lot of information but the die details are part of an >> optional table that is not implemented, hence we use a post parsing >> fixup hook to set the params->n_dice value manually. >> >> Link: https://www.winbond.com/resource-files/W25Q01JV%20SPI%20RevE%20030= 42024%20Plus.pdf >> Signed-off-by: Miquel Raynal >> --- >> >> Here is the basic test procedure output: >> >> $ cat /sys/bus/spi/devices/spi0.0/spi-nor/partname >> w25q01jv >> $ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id >> ef4021 >> $ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer >> winbond >> $ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp >> 53464450060101ff00060110800000ff84000102d00000ff03000102f000 >> 00ffffffffffffffffffffffffffffffffffffffffffffffffffffffffff >> ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff >> ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff >> ffffffffffffffffe520fbffffffff3f44eb086b083b42bbfeffffffffff >> 0000ffff40eb0c200f5210d800003602a60082ea14e2e96376337a757a75 >> f7a2d55c19f74dffe970f9a5ffffffffffffffffffffffffffffffffff0a >> f0ff21ffdcff >> $ md5sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp >> a7b9dbf76e99a33db99e557b6676588a /sys/bus/spi/devices/spi0.0/spi-nor/sf= dp >> $ dd if=3D/dev/urandom of=3D./qspi_test bs=3D1M count=3D1 >> 1+0 records in >> 1+0 records out >> $ mtd_debug write /dev/mtd0 0 1048576 qspi_test >> Copied 1048576 bytes from qspi_test to address 0x00000000 in flash >> $ mtd_debug erase /dev/mtd0 0 1048576 >> Erased 1048576 bytes from address 0x00000000 in flash >> $ mtd_debug read /dev/mtd0 0 1048576 qspi_read >> Copied 1048576 bytes from address 0x00000000 in flash to qspi_read >> $ hexdump qspi_read >> 0000000 ffff ffff ffff ffff ffff ffff ffff ffff >> * >> 0100000 >> $ mtd_debug write /dev/mtd0 0 1048576 qspi_test >> Copied 1048576 bytes from qspi_test to address 0x00000000 in flash >> $ mtd_debug read /dev/mtd0 0 1048576 qspi_read >> Copied 1048576 bytes from address 0x00000000 in flash to qspi_read >> $ sha1sum qspi_test qspi_read >> becf3097c0bbff0dd6f204ffe5bf575e6c43f792 qspi_test >> becf3097c0bbff0dd6f204ffe5bf575e6c43f792 qspi_read >> --- >> drivers/mtd/spi-nor/winbond.c | 82 ++++++++++++++++++++++++++++++++++++= +++++++ >> 1 file changed, 82 insertions(+) >> >> diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond= .c >> index 8d0a00d69e1233988876a15479d73c5fe899c542..4691e7a27ba1d70c75932c4e= 6b60fe36102138be 100644 >> --- a/drivers/mtd/spi-nor/winbond.c >> +++ b/drivers/mtd/spi-nor/winbond.c >> @@ -10,6 +10,7 @@ >>=20=20 >> #define WINBOND_NOR_OP_RDEAR 0xc8 /* Read Extended Address Register */ >> #define WINBOND_NOR_OP_WREAR 0xc5 /* Write Extended Address Register */ >> +#define WINBOND_NOR_OP_SELDIE 0xc2 /* Select active die */ >>=20=20 >> #define WINBOND_NOR_WREAR_OP(buf) \ >> SPI_MEM_OP(SPI_MEM_OP_CMD(WINBOND_NOR_OP_WREAR, 0), \ >> @@ -17,6 +18,12 @@ >> SPI_MEM_OP_NO_DUMMY, \ >> SPI_MEM_OP_DATA_OUT(1, buf, 0)) >>=20=20 >> +#define WINBOND_NOR_SELDIE_OP(buf) \ >> + SPI_MEM_OP(SPI_MEM_OP_CMD(WINBOND_NOR_OP_SELDIE, 0), \ >> + SPI_MEM_OP_NO_ADDR, \ >> + SPI_MEM_OP_NO_DUMMY, \ >> + SPI_MEM_OP_DATA_OUT(1, buf, 0)) >> + >> static int >> w25q128_post_bfpt_fixups(struct spi_nor *nor, >> const struct sfdp_parameter_header *bfpt_header, >> @@ -66,6 +73,26 @@ static const struct spi_nor_fixups w25q256_fixups =3D= { >> .post_bfpt =3D w25q256_post_bfpt_fixups, >> }; >>=20=20 >> +static int >> +w25q0xjv_post_bfpt_fixups(struct spi_nor *nor, >> + const struct sfdp_parameter_header *bfpt_header, >> + const struct sfdp_bfpt *bfpt) >> +{ >> + /* >> + * SFDP supports dice numbers, but this information is only available = in >> + * optional additional tables which are not provided by these chips. >> + * Dice number has an impact though, because these devices need extra >> + * care when reading the busy bit. >> + */ >> + nor->params->n_dice =3D nor->params->size / SZ_64M; > > n_dice is set by spi_nor_parse_sccr_mc(), which runs _after_ post-BFPT > fixups. This doesn't matter in practice since you say that the chip > doesn't have a SCCR_MC table but I think it still is a good idea to > follow the initialization order and do this in the post-SFDP hook. I must have been mislead by the names, indeed, I'll check. > >> + >> + return 0; >> +} >> + >> +static const struct spi_nor_fixups w25q0xjv_fixups =3D { >> + .post_bfpt =3D w25q0xjv_post_bfpt_fixups, >> +}; >> + >> static const struct flash_info winbond_nor_parts[] =3D { >> { >> .id =3D SNOR_ID(0xef, 0x30, 0x10), >> @@ -146,6 +173,11 @@ static const struct flash_info winbond_nor_parts[] = =3D { >> .name =3D "w25q512jvq", >> .size =3D SZ_64M, >> .no_sfdp_flags =3D SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, >> + }, { >> + .id =3D SNOR_ID(0xef, 0x40, 0x21), >> + .name =3D "w25q01jv", > > We no longer set the name for new flash entries. But knowing the flash > name for an entry is still useful, so make this a comment on top of the > entry. Actually without the flash entry the fixups cannot apply, so I'd expect any flash with fixups (like this one) to be listed at least? Said otherwise, what comment would you expect here? > >> + .no_sfdp_flags =3D SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, > > Since the flash has an SFDP table, you probably don't need these flags. > Can you try removing this line and see if things still work fine? Gasp. Second time I forget to remove these. Yes, this is a copy-paste left-over which is not needed. I'll double check it is actually not needed though. > >> + .fixups =3D &w25q0xjv_fixups, >> }, { >> .id =3D SNOR_ID(0xef, 0x50, 0x12), >> .name =3D "w25q20bw", >> @@ -289,6 +321,37 @@ static int winbond_nor_write_ear(struct spi_nor *no= r, u8 ear) >> return ret; >> } >>=20=20 >> +/** >> + * winbond_nor_select_die() - Set active die. >> + * @nor: pointer to 'struct spi_nor'. >> + * @die: die to set active. >> + * >> + * Return: 0 on success, -errno otherwise. >> + */ >> +static int winbond_nor_select_die(struct spi_nor *nor, u8 die) >> +{ >> + int ret; >> + >> + nor->bouncebuf[0] =3D die; >> + >> + if (nor->spimem) { >> + struct spi_mem_op op =3D WINBOND_NOR_SELDIE_OP(nor->bouncebuf); >> + >> + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); >> + >> + ret =3D spi_mem_exec_op(nor->spimem, &op); >> + } else { >> + ret =3D spi_nor_controller_ops_write_reg(nor, >> + WINBOND_NOR_OP_SELDIE, >> + nor->bouncebuf, 1); >> + } >> + >> + if (ret) >> + dev_dbg(nor->dev, "error %d selecting die %d\n", ret, die); >> + >> + return ret; >> +} >> + >> /** >> * winbond_nor_set_4byte_addr_mode() - Set 4-byte address mode for Winb= ond >> * flashes. >> @@ -322,6 +385,22 @@ static int winbond_nor_set_4byte_addr_mode(struct s= pi_nor *nor, bool enable) >> return spi_nor_write_disable(nor); >> } >>=20=20 > > Adding a short comment about why this is needed would be nice, and > readers won't always have to do a git blame to find out. Sure. > >> +static int winbond_multi_die_ready(struct spi_nor *nor) >> +{ >> + int ret, i; >> + >> + for (i =3D 0; i < nor->params->n_dice; i++) { >> + ret =3D winbond_nor_select_die(nor, i); >> + if (ret) >> + return ret; >> + >> + if (!spi_nor_sr_ready(nor)) > > spi_nor_sr_ready() can also return -errno, which would be treated here > as being ready, which obviously isn't right. This should also check for > a return value < 0. That's true. > >> + return 0; >> + } >> + >> + return 1; >> +} >> + >> static const struct spi_nor_otp_ops winbond_nor_otp_ops =3D { >> .read =3D spi_nor_otp_read_secr, >> .write =3D spi_nor_otp_write_secr, >> @@ -334,6 +413,9 @@ static int winbond_nor_late_init(struct spi_nor *nor) >> { >> struct spi_nor_flash_parameter *params =3D nor->params; >>=20=20 >> + if (params->n_dice > 1) >> + params->ready =3D winbond_multi_die_ready; >> + > > Is this true for all multi-die Winbond flashes, and going to hold true > for future ones? If not, I suppose this should go in the flash-specific > fixup hook. Do it in either the flash-specific late_init hook, or in the > post_sfdp hook, I have no strong opinions. This is an information hard to gather, I assumed it was always like that with Winbond flashes, I'll try to find more about it. Thanks for the review! Miqu=C3=A8l