From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18D331AA1FC; Mon, 11 Nov 2024 18:40:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731350438; cv=none; b=kO78CdTKBHc3kM8uiYJE+yfsW4Bpr0/ElI7CAN/9ih9xwdCazheUT2X3DSd4tdsTIGbJopbVZG4VPP/Wh+TPMEbc+fOLXbWiQ3FU6S7+xAmFwjuSQ0JpgTEJt8BwkJeqROKHco3SxiG90xZW+BGCARAi2U4ioEk6TJLBqTjo3Kg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731350438; c=relaxed/simple; bh=argA4IC79naaCW47Uh8xkDludQqNJZaYMhWC4/ygvdI=; h=From:To:Cc:Subject:In-Reply-To:Date:References:Message-ID: MIME-Version:Content-Type; b=XYCGKHBOgOvR9+puGLGptQGmwHnmQ2ifkreQcLyG964+X4NW+wWVTkArrX6WFH90SYj6nsYuaz6lsFvFKArFyildkwDH2l7qe/Zo/873lgkl52bi+yfDepIoOF7EtqbQO9/omWRDxNM+cHebghBLVI99+NSzex+3L6op2FCvdKg= ARC-Authentication-Results:i=1; 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bh=xbEusmclcP4bjdhemPuToxgTwCMcNFpEROLUhTJ3RqM=; b=iNVHac76RZ+QVrideqhJUALHc6nT2/gP3XxvPndIkdh4LYXxYBvL7VEcxjOLhQp++J6TQi wVmVTOinL0TVTwOow2oiiogXhcnnr69Y/Qqz1kA9uZy14r18NRuTraSw52JdnAkxdi24jV UaXPG5JueeNpg7YpJoDB5D9NiBVZKXtHw1Y1kqrLwn1lhoF+0T6y2+rAvI5+sC6YD21T0X 2fKuHfjZ+/OWCgAi/MyDdcoQat8edb5Sp16dHSncdo12nQMEiS9Kuv1xhdy5anVCmtwwAC hp9EHHE45GSCy+9JtXV3yNurkz/Z2Lx32kLAIaBGSWOWa8TWOGOq9yZunzaHag== From: Miquel Raynal To: Md Sadre Alam Cc: , , , , , , , , , , , , , , , Subject: Re: [PATCH v13 2/8] mtd: rawnand: qcom: cleanup qcom_nandc driver In-Reply-To: <20241030121919.865716-3-quic_mdalam@quicinc.com> (Md Sadre Alam's message of "Wed, 30 Oct 2024 17:49:13 +0530") Date: Mon, 11 Nov 2024 19:30:57 +0100 References: <20241030121919.865716-1-quic_mdalam@quicinc.com> <20241030121919.865716-3-quic_mdalam@quicinc.com> User-Agent: mu4e 1.12.1; emacs 29.4 Message-ID: <871pzh397j.fsf@bootlin.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: miquel.raynal@bootlin.com On 30/10/2024 at 17:49:13 +0530, Md Sadre Alam wr= ote: > cleanup qcom_nandc driver as below Perform a global cleanup of the Qualcomm NAND controller driver with the following improvements: > > - Remove register value indirection api API > > - Remove set_reg() api API > > - Convert read_loc_first & read_loc_last macro to function functions > > - Renamed multiple variables Rename ... > @@ -549,17 +535,17 @@ struct qcom_nand_host { > * among different NAND controllers. > * @ecc_modes - ecc mode for NAND > * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset > - * @is_bam - whether NAND controller is using BAM > - * @is_qpic - whether NAND CTRL is part of qpic IP > - * @qpic_v2 - flag to indicate QPIC IP version 2 > + * @supports_bam - whether NAND controller is using BAM Use the plain letters BAM acronym at least here > + * @nandc_part_of_qpic - whether NAND controller is part of qpic IP > + * @qpic_version2 - flag to indicate QPIC IP version 2 > * @use_codeword_fixup - whether NAND has different layout for boot part= itions > */ > struct qcom_nandc_props { > u32 ecc_modes; > u32 dev_cmd_reg_start; > - bool is_bam; > - bool is_qpic; > - bool qpic_v2; > + bool supports_bam; > + bool nandc_part_of_qpic; > + bool qpic_version2; > bool use_codeword_fixup; > }; >=20=20 > @@ -613,19 +599,11 @@ static void clear_bam_transaction(struct qcom_nand_= controller *nandc) > { > struct bam_transaction *bam_txn =3D nandc->bam_txn; >=20=20 > - if (!nandc->props->is_bam) > + if (!nandc->props->supports_bam) > return; >=20=20 > - bam_txn->bam_ce_pos =3D 0; > - bam_txn->bam_ce_start =3D 0; > - bam_txn->cmd_sgl_pos =3D 0; > - bam_txn->cmd_sgl_start =3D 0; > - bam_txn->tx_sgl_pos =3D 0; > - bam_txn->tx_sgl_start =3D 0; > - bam_txn->rx_sgl_pos =3D 0; > - bam_txn->rx_sgl_start =3D 0; > + memset(&bam_txn->bam_ce_pos, 0, sizeof(u32) * 8); > bam_txn->last_data_desc =3D NULL; > - bam_txn->wait_second_completion =3D false; >=20=20 > sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage * > QPIC_PER_CW_CMD_SGL); > @@ -640,17 +618,7 @@ static void qpic_bam_dma_done(void *data) > { > struct bam_transaction *bam_txn =3D data; >=20=20 > - /* > - * In case of data transfer with NAND, 2 callbacks will be generated. > - * One for command channel and another one for data channel. > - * If current transaction has data descriptors > - * (i.e. wait_second_completion is true), then set this to false > - * and wait for second DMA descriptor completion. > - */ > - if (bam_txn->wait_second_completion) > - bam_txn->wait_second_completion =3D false; > - else > - complete(&bam_txn->txn_done); > + complete(&bam_txn->txn_done); > } >=20=20 > static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip = *chip) > @@ -676,10 +644,9 @@ static inline void nandc_write(struct qcom_nand_cont= roller *nandc, int offset, > iowrite32(val, nandc->base + offset); > } >=20=20 > -static inline void nandc_read_buffer_sync(struct qcom_nand_controller *n= andc, > - bool is_cpu) > +static inline void nandc_dev_to_mem(struct qcom_nand_controller *nandc, = bool is_cpu) No static inline in C code, you can also remove it. > { > - if (!nandc->props->is_bam) > + if (!nandc->props->supports_bam) > return; >=20=20 > if (is_cpu) > @@ -694,93 +661,90 @@ static inline void nandc_read_buffer_sync(struct qc= om_nand_controller *nandc, > DMA_FROM_DEVICE); > } ... > +/* Helper to check the code word, whether it is last cw or not */ Helper to check whether this is the last CW or not > +static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw) > +{ > + return cw =3D=3D (ecc->steps - 1); > } >=20=20 > -static void nandc_set_reg(struct nand_chip *chip, int offset, > - u32 val) > +/** > + * nandc_set_read_loc_first() - to set read location first register > + * @chip: NAND Private Flash Chip Data > + * @reg_base: location register base > + * @cw_offset: code word offset > + * @read_size: code word read length > + * @is_last_read_loc: is this the last read location > + * > + * This function will set location register value > + */ ... > if (host->use_ecc) { > - cfg0 =3D (host->cfg0 & ~(7U << CW_PER_PAGE)) | > - (num_cw - 1) << CW_PER_PAGE; > + cfg0 =3D cpu_to_le32((host->cfg0 & ~(7U << CW_PER_PAGE)) | > + (num_cw - 1) << CW_PER_PAGE); >=20=20 > - cfg1 =3D host->cfg1; > - ecc_bch_cfg =3D host->ecc_bch_cfg; > + cfg1 =3D cpu_to_le32(host->cfg1); > + ecc_bch_cfg =3D cpu_to_le32(host->ecc_bch_cfg); > } else { > - cfg0 =3D (host->cfg0_raw & ~(7U << CW_PER_PAGE)) | > - (num_cw - 1) << CW_PER_PAGE; > + cfg0 =3D cpu_to_le32((host->cfg0_raw & ~(7U << CW_PER_PAGE)) | > + (num_cw - 1) << CW_PER_PAGE); >=20=20 > - cfg1 =3D host->cfg1_raw; > - ecc_bch_cfg =3D 1 << ECC_CFG_ECC_DISABLE; > + cfg1 =3D cpu_to_le32(host->cfg1_raw); > + ecc_bch_cfg =3D cpu_to_le32(1 << ECC_CFG_ECC_DISABLE); > } >=20=20 > - nandc_set_reg(chip, NAND_FLASH_CMD, cmd); > - nandc_set_reg(chip, NAND_DEV0_CFG0, cfg0); > - nandc_set_reg(chip, NAND_DEV0_CFG1, cfg1); > - nandc_set_reg(chip, NAND_DEV0_ECC_CFG, ecc_bch_cfg); > - if (!nandc->props->qpic_v2) > - nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg); > - nandc_set_reg(chip, NAND_FLASH_STATUS, host->clrflashstatus); > - nandc_set_reg(chip, NAND_READ_STATUS, host->clrreadstatus); > - nandc_set_reg(chip, NAND_EXEC_CMD, 1); > + nandc->regs->cmd =3D cmd; > + nandc->regs->cfg0 =3D cfg0; > + nandc->regs->cfg1 =3D cfg1; > + nandc->regs->ecc_bch_cfg =3D ecc_bch_cfg; > + > + if (!nandc->props->qpic_version2) > + nandc->regs->ecc_buf_cfg =3D cpu_to_le32(host->ecc_buf_cfg); > + > + nandc->regs->clrflashstatus =3D cpu_to_le32(host->clrflashstatus); > + nandc->regs->clrreadstatus =3D cpu_to_le32(host->clrreadstatus); > + nandc->regs->exec =3D cpu_to_le32(1); >=20=20 > if (read) > nandc_set_read_loc(chip, cw, 0, 0, host->use_ecc ? > @@ -1121,7 +1088,7 @@ static int read_reg_dma(struct qcom_nand_controller= *nandc, int first, > if (first =3D=3D NAND_DEV_CMD_VLD || first =3D=3D NAND_DEV_CMD1) > first =3D dev_cmd_reg_addr(nandc, first); >=20=20 > - if (nandc->props->is_bam) > + if (nandc->props->supports_bam) > return prep_bam_dma_desc_cmd(nandc, true, first, vaddr, > num_regs, flags); >=20=20 > @@ -1136,25 +1103,16 @@ static int read_reg_dma(struct qcom_nand_controll= er *nandc, int first, > * write_reg_dma: prepares a descriptor to write a given number of > * contiguous registers > * > + * @vaddr: contnigeous memory from where register value > will Please run a spell checker on your commits. > + * be written > * @first: offset of the first register in the contiguous block > * @num_regs: number of registers to write > * @flags: flags to control DMA descriptor preparation > */ > -static int write_reg_dma(struct qcom_nand_controller *nandc, int first, > - int num_regs, unsigned int flags) > +static int write_reg_dma(struct qcom_nand_controller *nandc, __le32 *vad= dr, > + int first, int num_regs, unsigned int flags) > { > bool flow_control =3D false; > - struct nandc_regs *regs =3D nandc->regs; > - void *vaddr; > - > - vaddr =3D offset_to_nandc_reg(regs, first); > - > - if (first =3D=3D NAND_ERASED_CW_DETECT_CFG) { > - if (flags & NAND_ERASED_CW_SET) > - vaddr =3D ®s->erased_cw_detect_cfg_set; > - else > - vaddr =3D ®s->erased_cw_detect_cfg_clr; > - } >=20=20 > if (first =3D=3D NAND_EXEC_CMD) > flags |=3D NAND_BAM_NWD; > @@ -1165,7 +1123,7 @@ static int write_reg_dma(struct qcom_nand_controlle= r *nandc, int first, > if (first =3D=3D NAND_DEV_CMD_VLD_RESTORE || first =3D=3D NAND_DEV_CMD_= VLD) > first =3D dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD); >=20=20 > - if (nandc->props->is_bam) > + if (nandc->props->supports_bam) > return prep_bam_dma_desc_cmd(nandc, false, first, vaddr, > num_regs, flags); >=20=20 ... > @@ -2872,38 +2823,38 @@ static int qcom_param_page_type_exec(struct nand_= chip *chip, const struct nand_ > clear_read_regs(nandc); > clear_bam_transaction(nandc); >=20=20 > - nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg); > - > - nandc_set_reg(chip, NAND_ADDR0, 0); > - nandc_set_reg(chip, NAND_ADDR1, 0); > - nandc_set_reg(chip, NAND_DEV0_CFG0, 0 << CW_PER_PAGE > - | 512 << UD_SIZE_BYTES > - | 5 << NUM_ADDR_CYCLES > - | 0 << SPARE_SIZE_BYTES); > - nandc_set_reg(chip, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES > - | 0 << CS_ACTIVE_BSY > - | 17 << BAD_BLOCK_BYTE_NUM > - | 1 << BAD_BLOCK_IN_SPARE_AREA > - | 2 << WR_RD_BSY_GAP > - | 0 << WIDE_FLASH > - | 1 << DEV0_CFG1_ECC_DISABLE); Please fix the coding style. The '|' should be at the end of the line. Thanks, Miqu=C3=A8l From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED62FD3ABEB for ; Mon, 11 Nov 2024 18:40:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:References:Date :In-Reply-To:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=C0fObBCpti58yHvuX76HKQItDRpZ0M5zN8L7Itcwa6Y=; b=ktGlGV7lLqz67h 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h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xbEusmclcP4bjdhemPuToxgTwCMcNFpEROLUhTJ3RqM=; b=iNVHac76RZ+QVrideqhJUALHc6nT2/gP3XxvPndIkdh4LYXxYBvL7VEcxjOLhQp++J6TQi wVmVTOinL0TVTwOow2oiiogXhcnnr69Y/Qqz1kA9uZy14r18NRuTraSw52JdnAkxdi24jV UaXPG5JueeNpg7YpJoDB5D9NiBVZKXtHw1Y1kqrLwn1lhoF+0T6y2+rAvI5+sC6YD21T0X 2fKuHfjZ+/OWCgAi/MyDdcoQat8edb5Sp16dHSncdo12nQMEiS9Kuv1xhdy5anVCmtwwAC hp9EHHE45GSCy+9JtXV3yNurkz/Z2Lx32kLAIaBGSWOWa8TWOGOq9yZunzaHag== From: Miquel Raynal To: Md Sadre Alam Cc: , , , , , , , , , , , , , , , Subject: Re: [PATCH v13 2/8] mtd: rawnand: qcom: cleanup qcom_nandc driver In-Reply-To: <20241030121919.865716-3-quic_mdalam@quicinc.com> (Md Sadre Alam's message of "Wed, 30 Oct 2024 17:49:13 +0530") Date: Mon, 11 Nov 2024 19:30:57 +0100 References: <20241030121919.865716-1-quic_mdalam@quicinc.com> <20241030121919.865716-3-quic_mdalam@quicinc.com> User-Agent: mu4e 1.12.1; emacs 29.4 Message-ID: <871pzh397j.fsf@bootlin.com> MIME-Version: 1.0 X-GND-Sasl: miquel.raynal@bootlin.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241111_104036_802844_FABCBF60 X-CRM114-Status: GOOD ( 27.14 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org T24gMzAvMTAvMjAyNCBhdCAxNzo0OToxMyArMDUzMCwgTWQgU2FkcmUgQWxhbSA8cXVpY19tZGFs YW1AcXVpY2luYy5jb20+IHdyb3RlOgoKPiBjbGVhbnVwIHFjb21fbmFuZGMgZHJpdmVyIGFzIGJl bG93CgpQZXJmb3JtIGEgZ2xvYmFsIGNsZWFudXAgb2YgdGhlIFF1YWxjb21tIE5BTkQgY29udHJv bGxlciBkcml2ZXIgd2l0aCB0aGUKZm9sbG93aW5nIGltcHJvdmVtZW50czoKPgo+IC0gUmVtb3Zl IHJlZ2lzdGVyIHZhbHVlIGluZGlyZWN0aW9uIGFwaQoKQVBJCgo+Cj4gLSBSZW1vdmUgc2V0X3Jl ZygpIGFwaQoKQVBJCgo+Cj4gLSBDb252ZXJ0IHJlYWRfbG9jX2ZpcnN0ICYgcmVhZF9sb2NfbGFz dCBtYWNybyB0byBmdW5jdGlvbgoKZnVuY3Rpb25zCgo+Cj4gLSBSZW5hbWVkIG11bHRpcGxlIHZh cmlhYmxlcwoKUmVuYW1lCgouLi4KCj4gQEAgLTU0OSwxNyArNTM1LDE3IEBAIHN0cnVjdCBxY29t X25hbmRfaG9zdCB7Cj4gICAqIGFtb25nIGRpZmZlcmVudCBOQU5EIGNvbnRyb2xsZXJzLgo+ICAg KiBAZWNjX21vZGVzIC0gZWNjIG1vZGUgZm9yIE5BTkQKPiAgICogQGRldl9jbWRfcmVnX3N0YXJ0 IC0gTkFORF9ERVZfQ01EXyogcmVnaXN0ZXJzIHN0YXJ0aW5nIG9mZnNldAo+IC0gKiBAaXNfYmFt IC0gd2hldGhlciBOQU5EIGNvbnRyb2xsZXIgaXMgdXNpbmcgQkFNCj4gLSAqIEBpc19xcGljIC0g d2hldGhlciBOQU5EIENUUkwgaXMgcGFydCBvZiBxcGljIElQCj4gLSAqIEBxcGljX3YyIC0gZmxh ZyB0byBpbmRpY2F0ZSBRUElDIElQIHZlcnNpb24gMgo+ICsgKiBAc3VwcG9ydHNfYmFtIC0gd2hl dGhlciBOQU5EIGNvbnRyb2xsZXIgaXMgdXNpbmcgQkFNCgpVc2UgdGhlIHBsYWluIGxldHRlcnMg QkFNIGFjcm9ueW0gYXQgbGVhc3QgaGVyZQoKPiArICogQG5hbmRjX3BhcnRfb2ZfcXBpYyAtIHdo ZXRoZXIgTkFORCBjb250cm9sbGVyIGlzIHBhcnQgb2YgcXBpYyBJUAo+ICsgKiBAcXBpY192ZXJz aW9uMiAtIGZsYWcgdG8gaW5kaWNhdGUgUVBJQyBJUCB2ZXJzaW9uIDIKPiAgICogQHVzZV9jb2Rl d29yZF9maXh1cCAtIHdoZXRoZXIgTkFORCBoYXMgZGlmZmVyZW50IGxheW91dCBmb3IgYm9vdCBw YXJ0aXRpb25zCj4gICAqLwo+ICBzdHJ1Y3QgcWNvbV9uYW5kY19wcm9wcyB7Cj4gIAl1MzIgZWNj X21vZGVzOwo+ICAJdTMyIGRldl9jbWRfcmVnX3N0YXJ0Owo+IC0JYm9vbCBpc19iYW07Cj4gLQli b29sIGlzX3FwaWM7Cj4gLQlib29sIHFwaWNfdjI7Cj4gKwlib29sIHN1cHBvcnRzX2JhbTsKPiAr CWJvb2wgbmFuZGNfcGFydF9vZl9xcGljOwo+ICsJYm9vbCBxcGljX3ZlcnNpb24yOwo+ICAJYm9v bCB1c2VfY29kZXdvcmRfZml4dXA7Cj4gIH07Cj4gIAo+IEBAIC02MTMsMTkgKzU5OSwxMSBAQCBz dGF0aWMgdm9pZCBjbGVhcl9iYW1fdHJhbnNhY3Rpb24oc3RydWN0IHFjb21fbmFuZF9jb250cm9s bGVyICpuYW5kYykKPiAgewo+ICAJc3RydWN0IGJhbV90cmFuc2FjdGlvbiAqYmFtX3R4biA9IG5h bmRjLT5iYW1fdHhuOwo+ICAKPiAtCWlmICghbmFuZGMtPnByb3BzLT5pc19iYW0pCj4gKwlpZiAo IW5hbmRjLT5wcm9wcy0+c3VwcG9ydHNfYmFtKQo+ICAJCXJldHVybjsKPiAgCj4gLQliYW1fdHhu LT5iYW1fY2VfcG9zID0gMDsKPiAtCWJhbV90eG4tPmJhbV9jZV9zdGFydCA9IDA7Cj4gLQliYW1f dHhuLT5jbWRfc2dsX3BvcyA9IDA7Cj4gLQliYW1fdHhuLT5jbWRfc2dsX3N0YXJ0ID0gMDsKPiAt CWJhbV90eG4tPnR4X3NnbF9wb3MgPSAwOwo+IC0JYmFtX3R4bi0+dHhfc2dsX3N0YXJ0ID0gMDsK PiAtCWJhbV90eG4tPnJ4X3NnbF9wb3MgPSAwOwo+IC0JYmFtX3R4bi0+cnhfc2dsX3N0YXJ0ID0g MDsKPiArCW1lbXNldCgmYmFtX3R4bi0+YmFtX2NlX3BvcywgMCwgc2l6ZW9mKHUzMikgKiA4KTsK PiAgCWJhbV90eG4tPmxhc3RfZGF0YV9kZXNjID0gTlVMTDsKPiAtCWJhbV90eG4tPndhaXRfc2Vj b25kX2NvbXBsZXRpb24gPSBmYWxzZTsKPiAgCj4gIAlzZ19pbml0X3RhYmxlKGJhbV90eG4tPmNt ZF9zZ2wsIG5hbmRjLT5tYXhfY3dwZXJwYWdlICoKPiAgCQkgICAgICBRUElDX1BFUl9DV19DTURf U0dMKTsKPiBAQCAtNjQwLDE3ICs2MTgsNyBAQCBzdGF0aWMgdm9pZCBxcGljX2JhbV9kbWFfZG9u ZSh2b2lkICpkYXRhKQo+ICB7Cj4gIAlzdHJ1Y3QgYmFtX3RyYW5zYWN0aW9uICpiYW1fdHhuID0g ZGF0YTsKPiAgCj4gLQkvKgo+IC0JICogSW4gY2FzZSBvZiBkYXRhIHRyYW5zZmVyIHdpdGggTkFO RCwgMiBjYWxsYmFja3Mgd2lsbCBiZSBnZW5lcmF0ZWQuCj4gLQkgKiBPbmUgZm9yIGNvbW1hbmQg Y2hhbm5lbCBhbmQgYW5vdGhlciBvbmUgZm9yIGRhdGEgY2hhbm5lbC4KPiAtCSAqIElmIGN1cnJl bnQgdHJhbnNhY3Rpb24gaGFzIGRhdGEgZGVzY3JpcHRvcnMKPiAtCSAqIChpLmUuIHdhaXRfc2Vj b25kX2NvbXBsZXRpb24gaXMgdHJ1ZSksIHRoZW4gc2V0IHRoaXMgdG8gZmFsc2UKPiAtCSAqIGFu ZCB3YWl0IGZvciBzZWNvbmQgRE1BIGRlc2NyaXB0b3IgY29tcGxldGlvbi4KPiAtCSAqLwo+IC0J aWYgKGJhbV90eG4tPndhaXRfc2Vjb25kX2NvbXBsZXRpb24pCj4gLQkJYmFtX3R4bi0+d2FpdF9z ZWNvbmRfY29tcGxldGlvbiA9IGZhbHNlOwo+IC0JZWxzZQo+IC0JCWNvbXBsZXRlKCZiYW1fdHhu LT50eG5fZG9uZSk7Cj4gKwljb21wbGV0ZSgmYmFtX3R4bi0+dHhuX2RvbmUpOwo+ICB9Cj4gIAo+ ICBzdGF0aWMgaW5saW5lIHN0cnVjdCBxY29tX25hbmRfaG9zdCAqdG9fcWNvbV9uYW5kX2hvc3Qo c3RydWN0IG5hbmRfY2hpcCAqY2hpcCkKPiBAQCAtNjc2LDEwICs2NDQsOSBAQCBzdGF0aWMgaW5s aW5lIHZvaWQgbmFuZGNfd3JpdGUoc3RydWN0IHFjb21fbmFuZF9jb250cm9sbGVyICpuYW5kYywg aW50IG9mZnNldCwKPiAgCWlvd3JpdGUzMih2YWwsIG5hbmRjLT5iYXNlICsgb2Zmc2V0KTsKPiAg fQo+ICAKPiAtc3RhdGljIGlubGluZSB2b2lkIG5hbmRjX3JlYWRfYnVmZmVyX3N5bmMoc3RydWN0 IHFjb21fbmFuZF9jb250cm9sbGVyICpuYW5kYywKPiAtCQkJCQkgIGJvb2wgaXNfY3B1KQo+ICtz dGF0aWMgaW5saW5lIHZvaWQgbmFuZGNfZGV2X3RvX21lbShzdHJ1Y3QgcWNvbV9uYW5kX2NvbnRy b2xsZXIgKm5hbmRjLCBib29sIGlzX2NwdSkKCk5vIHN0YXRpYyBpbmxpbmUgaW4gQyBjb2RlLCB5 b3UgY2FuIGFsc28gcmVtb3ZlIGl0LgoKPiAgewo+IC0JaWYgKCFuYW5kYy0+cHJvcHMtPmlzX2Jh bSkKPiArCWlmICghbmFuZGMtPnByb3BzLT5zdXBwb3J0c19iYW0pCj4gIAkJcmV0dXJuOwo+ICAK PiAgCWlmIChpc19jcHUpCj4gQEAgLTY5NCw5MyArNjYxLDkwIEBAIHN0YXRpYyBpbmxpbmUgdm9p ZCBuYW5kY19yZWFkX2J1ZmZlcl9zeW5jKHN0cnVjdCBxY29tX25hbmRfY29udHJvbGxlciAqbmFu ZGMsCj4gIAkJCQkJICAgRE1BX0ZST01fREVWSUNFKTsKPiAgfQoKLi4uCgo+ICsvKiBIZWxwZXIg dG8gY2hlY2sgdGhlIGNvZGUgd29yZCwgd2hldGhlciBpdCBpcyBsYXN0IGN3IG9yIG5vdCAqLwoK SGVscGVyIHRvIGNoZWNrIHdoZXRoZXIgdGhpcyBpcyB0aGUgbGFzdCBDVyBvciBub3QKCgo+ICtz dGF0aWMgYm9vbCBxY29tX25hbmRjX2lzX2xhc3RfY3coc3RydWN0IG5hbmRfZWNjX2N0cmwgKmVj YywgaW50IGN3KQo+ICt7Cj4gKwlyZXR1cm4gY3cgPT0gKGVjYy0+c3RlcHMgLSAxKTsKPiAgfQo+ ICAKPiAtc3RhdGljIHZvaWQgbmFuZGNfc2V0X3JlZyhzdHJ1Y3QgbmFuZF9jaGlwICpjaGlwLCBp bnQgb2Zmc2V0LAo+IC0JCQkgIHUzMiB2YWwpCj4gKy8qKgo+ICsgKiBuYW5kY19zZXRfcmVhZF9s b2NfZmlyc3QoKSAtIHRvIHNldCByZWFkIGxvY2F0aW9uIGZpcnN0IHJlZ2lzdGVyCj4gKyAqIEBj aGlwOgkJTkFORCBQcml2YXRlIEZsYXNoIENoaXAgRGF0YQo+ICsgKiBAcmVnX2Jhc2U6CQlsb2Nh dGlvbiByZWdpc3RlciBiYXNlCj4gKyAqIEBjd19vZmZzZXQ6CQljb2RlIHdvcmQgb2Zmc2V0Cj4g KyAqIEByZWFkX3NpemU6CQljb2RlIHdvcmQgcmVhZCBsZW5ndGgKPiArICogQGlzX2xhc3RfcmVh ZF9sb2M6CWlzIHRoaXMgdGhlIGxhc3QgcmVhZCBsb2NhdGlvbgo+ICsgKgo+ICsgKiBUaGlzIGZ1 bmN0aW9uIHdpbGwgc2V0IGxvY2F0aW9uIHJlZ2lzdGVyIHZhbHVlCj4gKyAqLwoKLi4uCgo+ICAJ aWYgKGhvc3QtPnVzZV9lY2MpIHsKPiAtCQljZmcwID0gKGhvc3QtPmNmZzAgJiB+KDdVIDw8IENX X1BFUl9QQUdFKSkgfAo+IC0JCQkJKG51bV9jdyAtIDEpIDw8IENXX1BFUl9QQUdFOwo+ICsJCWNm ZzAgPSBjcHVfdG9fbGUzMigoaG9zdC0+Y2ZnMCAmIH4oN1UgPDwgQ1dfUEVSX1BBR0UpKSB8Cj4g KwkJCQkobnVtX2N3IC0gMSkgPDwgQ1dfUEVSX1BBR0UpOwo+ICAKPiAtCQljZmcxID0gaG9zdC0+ Y2ZnMTsKPiAtCQllY2NfYmNoX2NmZyA9IGhvc3QtPmVjY19iY2hfY2ZnOwo+ICsJCWNmZzEgPSBj cHVfdG9fbGUzMihob3N0LT5jZmcxKTsKPiArCQllY2NfYmNoX2NmZyA9IGNwdV90b19sZTMyKGhv c3QtPmVjY19iY2hfY2ZnKTsKPiAgCX0gZWxzZSB7Cj4gLQkJY2ZnMCA9IChob3N0LT5jZmcwX3Jh dyAmIH4oN1UgPDwgQ1dfUEVSX1BBR0UpKSB8Cj4gLQkJCQkobnVtX2N3IC0gMSkgPDwgQ1dfUEVS X1BBR0U7Cj4gKwkJY2ZnMCA9IGNwdV90b19sZTMyKChob3N0LT5jZmcwX3JhdyAmIH4oN1UgPDwg Q1dfUEVSX1BBR0UpKSB8Cj4gKwkJCQkobnVtX2N3IC0gMSkgPDwgQ1dfUEVSX1BBR0UpOwo+ICAK PiAtCQljZmcxID0gaG9zdC0+Y2ZnMV9yYXc7Cj4gLQkJZWNjX2JjaF9jZmcgPSAxIDw8IEVDQ19D RkdfRUNDX0RJU0FCTEU7Cj4gKwkJY2ZnMSA9IGNwdV90b19sZTMyKGhvc3QtPmNmZzFfcmF3KTsK PiArCQllY2NfYmNoX2NmZyA9IGNwdV90b19sZTMyKDEgPDwgRUNDX0NGR19FQ0NfRElTQUJMRSk7 Cj4gIAl9Cj4gIAo+IC0JbmFuZGNfc2V0X3JlZyhjaGlwLCBOQU5EX0ZMQVNIX0NNRCwgY21kKTsK PiAtCW5hbmRjX3NldF9yZWcoY2hpcCwgTkFORF9ERVYwX0NGRzAsIGNmZzApOwo+IC0JbmFuZGNf c2V0X3JlZyhjaGlwLCBOQU5EX0RFVjBfQ0ZHMSwgY2ZnMSk7Cj4gLQluYW5kY19zZXRfcmVnKGNo aXAsIE5BTkRfREVWMF9FQ0NfQ0ZHLCBlY2NfYmNoX2NmZyk7Cj4gLQlpZiAoIW5hbmRjLT5wcm9w cy0+cXBpY192MikKPiAtCQluYW5kY19zZXRfcmVnKGNoaXAsIE5BTkRfRUJJMl9FQ0NfQlVGX0NG RywgaG9zdC0+ZWNjX2J1Zl9jZmcpOwo+IC0JbmFuZGNfc2V0X3JlZyhjaGlwLCBOQU5EX0ZMQVNI X1NUQVRVUywgaG9zdC0+Y2xyZmxhc2hzdGF0dXMpOwo+IC0JbmFuZGNfc2V0X3JlZyhjaGlwLCBO QU5EX1JFQURfU1RBVFVTLCBob3N0LT5jbHJyZWFkc3RhdHVzKTsKPiAtCW5hbmRjX3NldF9yZWco Y2hpcCwgTkFORF9FWEVDX0NNRCwgMSk7Cj4gKwluYW5kYy0+cmVncy0+Y21kID0gY21kOwo+ICsJ bmFuZGMtPnJlZ3MtPmNmZzAgPSBjZmcwOwo+ICsJbmFuZGMtPnJlZ3MtPmNmZzEgPSBjZmcxOwo+ ICsJbmFuZGMtPnJlZ3MtPmVjY19iY2hfY2ZnID0gZWNjX2JjaF9jZmc7Cj4gKwo+ICsJaWYgKCFu YW5kYy0+cHJvcHMtPnFwaWNfdmVyc2lvbjIpCj4gKwkJbmFuZGMtPnJlZ3MtPmVjY19idWZfY2Zn ID0gY3B1X3RvX2xlMzIoaG9zdC0+ZWNjX2J1Zl9jZmcpOwo+ICsKPiArCW5hbmRjLT5yZWdzLT5j bHJmbGFzaHN0YXR1cyA9IGNwdV90b19sZTMyKGhvc3QtPmNscmZsYXNoc3RhdHVzKTsKPiArCW5h bmRjLT5yZWdzLT5jbHJyZWFkc3RhdHVzID0gY3B1X3RvX2xlMzIoaG9zdC0+Y2xycmVhZHN0YXR1 cyk7Cj4gKwluYW5kYy0+cmVncy0+ZXhlYyA9IGNwdV90b19sZTMyKDEpOwo+ICAKPiAgCWlmIChy ZWFkKQo+ICAJCW5hbmRjX3NldF9yZWFkX2xvYyhjaGlwLCBjdywgMCwgMCwgaG9zdC0+dXNlX2Vj YyA/Cj4gQEAgLTExMjEsNyArMTA4OCw3IEBAIHN0YXRpYyBpbnQgcmVhZF9yZWdfZG1hKHN0cnVj dCBxY29tX25hbmRfY29udHJvbGxlciAqbmFuZGMsIGludCBmaXJzdCwKPiAgCWlmIChmaXJzdCA9 PSBOQU5EX0RFVl9DTURfVkxEIHx8IGZpcnN0ID09IE5BTkRfREVWX0NNRDEpCj4gIAkJZmlyc3Qg PSBkZXZfY21kX3JlZ19hZGRyKG5hbmRjLCBmaXJzdCk7Cj4gIAo+IC0JaWYgKG5hbmRjLT5wcm9w cy0+aXNfYmFtKQo+ICsJaWYgKG5hbmRjLT5wcm9wcy0+c3VwcG9ydHNfYmFtKQo+ICAJCXJldHVy biBwcmVwX2JhbV9kbWFfZGVzY19jbWQobmFuZGMsIHRydWUsIGZpcnN0LCB2YWRkciwKPiAgCQkJ CQkgICAgIG51bV9yZWdzLCBmbGFncyk7Cj4gIAo+IEBAIC0xMTM2LDI1ICsxMTAzLDE2IEBAIHN0 YXRpYyBpbnQgcmVhZF9yZWdfZG1hKHN0cnVjdCBxY29tX25hbmRfY29udHJvbGxlciAqbmFuZGMs IGludCBmaXJzdCwKPiAgICogd3JpdGVfcmVnX2RtYToJcHJlcGFyZXMgYSBkZXNjcmlwdG9yIHRv IHdyaXRlIGEgZ2l2ZW4gbnVtYmVyIG9mCj4gICAqCQkJY29udGlndW91cyByZWdpc3RlcnMKPiAg ICoKPiArICogQHZhZGRyOgkJY29udG5pZ2VvdXMgbWVtb3J5IGZyb20gd2hlcmUgcmVnaXN0ZXIg dmFsdWUKPiB3aWxsCgpQbGVhc2UgcnVuIGEgc3BlbGwgY2hlY2tlciBvbiB5b3VyIGNvbW1pdHMu Cgo+ICsgKgkJCWJlIHdyaXR0ZW4KPiAgICogQGZpcnN0OgkJb2Zmc2V0IG9mIHRoZSBmaXJzdCBy ZWdpc3RlciBpbiB0aGUgY29udGlndW91cyBibG9jawo+ICAgKiBAbnVtX3JlZ3M6CQludW1iZXIg b2YgcmVnaXN0ZXJzIHRvIHdyaXRlCj4gICAqIEBmbGFnczoJCWZsYWdzIHRvIGNvbnRyb2wgRE1B IGRlc2NyaXB0b3IgcHJlcGFyYXRpb24KPiAgICovCj4gLXN0YXRpYyBpbnQgd3JpdGVfcmVnX2Rt YShzdHJ1Y3QgcWNvbV9uYW5kX2NvbnRyb2xsZXIgKm5hbmRjLCBpbnQgZmlyc3QsCj4gLQkJCSBp bnQgbnVtX3JlZ3MsIHVuc2lnbmVkIGludCBmbGFncykKPiArc3RhdGljIGludCB3cml0ZV9yZWdf ZG1hKHN0cnVjdCBxY29tX25hbmRfY29udHJvbGxlciAqbmFuZGMsIF9fbGUzMiAqdmFkZHIsCj4g KwkJCSBpbnQgZmlyc3QsIGludCBudW1fcmVncywgdW5zaWduZWQgaW50IGZsYWdzKQo+ICB7Cj4g IAlib29sIGZsb3dfY29udHJvbCA9IGZhbHNlOwo+IC0Jc3RydWN0IG5hbmRjX3JlZ3MgKnJlZ3Mg PSBuYW5kYy0+cmVnczsKPiAtCXZvaWQgKnZhZGRyOwo+IC0KPiAtCXZhZGRyID0gb2Zmc2V0X3Rv X25hbmRjX3JlZyhyZWdzLCBmaXJzdCk7Cj4gLQo+IC0JaWYgKGZpcnN0ID09IE5BTkRfRVJBU0VE X0NXX0RFVEVDVF9DRkcpIHsKPiAtCQlpZiAoZmxhZ3MgJiBOQU5EX0VSQVNFRF9DV19TRVQpCj4g LQkJCXZhZGRyID0gJnJlZ3MtPmVyYXNlZF9jd19kZXRlY3RfY2ZnX3NldDsKPiAtCQllbHNlCj4g LQkJCXZhZGRyID0gJnJlZ3MtPmVyYXNlZF9jd19kZXRlY3RfY2ZnX2NscjsKPiAtCX0KPiAgCj4g IAlpZiAoZmlyc3QgPT0gTkFORF9FWEVDX0NNRCkKPiAgCQlmbGFncyB8PSBOQU5EX0JBTV9OV0Q7 Cj4gQEAgLTExNjUsNyArMTEyMyw3IEBAIHN0YXRpYyBpbnQgd3JpdGVfcmVnX2RtYShzdHJ1Y3Qg cWNvbV9uYW5kX2NvbnRyb2xsZXIgKm5hbmRjLCBpbnQgZmlyc3QsCj4gIAlpZiAoZmlyc3QgPT0g TkFORF9ERVZfQ01EX1ZMRF9SRVNUT1JFIHx8IGZpcnN0ID09IE5BTkRfREVWX0NNRF9WTEQpCj4g IAkJZmlyc3QgPSBkZXZfY21kX3JlZ19hZGRyKG5hbmRjLCBOQU5EX0RFVl9DTURfVkxEKTsKPiAg Cj4gLQlpZiAobmFuZGMtPnByb3BzLT5pc19iYW0pCj4gKwlpZiAobmFuZGMtPnByb3BzLT5zdXBw b3J0c19iYW0pCj4gIAkJcmV0dXJuIHByZXBfYmFtX2RtYV9kZXNjX2NtZChuYW5kYywgZmFsc2Us IGZpcnN0LCB2YWRkciwKPiAgCQkJCQkgICAgIG51bV9yZWdzLCBmbGFncyk7Cj4gIAoKLi4uCgo+ IEBAIC0yODcyLDM4ICsyODIzLDM4IEBAIHN0YXRpYyBpbnQgcWNvbV9wYXJhbV9wYWdlX3R5cGVf ZXhlYyhzdHJ1Y3QgbmFuZF9jaGlwICpjaGlwLCAgY29uc3Qgc3RydWN0IG5hbmRfCj4gIAljbGVh cl9yZWFkX3JlZ3MobmFuZGMpOwo+ICAJY2xlYXJfYmFtX3RyYW5zYWN0aW9uKG5hbmRjKTsKPiAg Cj4gLQluYW5kY19zZXRfcmVnKGNoaXAsIE5BTkRfRkxBU0hfQ01ELCBxX29wLmNtZF9yZWcpOwo+ IC0KPiAtCW5hbmRjX3NldF9yZWcoY2hpcCwgTkFORF9BRERSMCwgMCk7Cj4gLQluYW5kY19zZXRf cmVnKGNoaXAsIE5BTkRfQUREUjEsIDApOwo+IC0JbmFuZGNfc2V0X3JlZyhjaGlwLCBOQU5EX0RF VjBfQ0ZHMCwgMCA8PCBDV19QRVJfUEFHRQo+IC0JCQkJCXwgNTEyIDw8IFVEX1NJWkVfQllURVMK PiAtCQkJCQl8IDUgPDwgTlVNX0FERFJfQ1lDTEVTCj4gLQkJCQkJfCAwIDw8IFNQQVJFX1NJWkVf QllURVMpOwo+IC0JbmFuZGNfc2V0X3JlZyhjaGlwLCBOQU5EX0RFVjBfQ0ZHMSwgNyA8PCBOQU5E X1JFQ09WRVJZX0NZQ0xFUwo+IC0JCQkJCXwgMCA8PCBDU19BQ1RJVkVfQlNZCj4gLQkJCQkJfCAx NyA8PCBCQURfQkxPQ0tfQllURV9OVU0KPiAtCQkJCQl8IDEgPDwgQkFEX0JMT0NLX0lOX1NQQVJF X0FSRUEKPiAtCQkJCQl8IDIgPDwgV1JfUkRfQlNZX0dBUAo+IC0JCQkJCXwgMCA8PCBXSURFX0ZM QVNICj4gLQkJCQkJfCAxIDw8IERFVjBfQ0ZHMV9FQ0NfRElTQUJMRSk7CgpQbGVhc2UgZml4IHRo ZSBjb2Rpbmcgc3R5bGUuIFRoZSAnfCcgc2hvdWxkIGJlIGF0IHRoZSBlbmQgb2YgdGhlIGxpbmUu CgpUaGFua3MsCk1pcXXDqGwKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fXwpMaW51eCBNVEQgZGlzY3Vzc2lvbiBtYWlsaW5nIGxpc3QKaHR0cDov L2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1tdGQvCg==