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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Nirmoy Das <nirmoy.das@intel.com>, intel-xe@lists.freedesktop.org
Cc: "Nirmoy Das" <nirmoy.das@intel.com>,
	"Matthew Auld" <matthew.auld@intel.com>,
	"Matthew Brost" <matthew.brost@intel.com>,
	"Thomas Hellström" <thomas.hellstrom@linux.intel.com>
Subject: Re: [PATCH 1/2] drm/xe: Skip CCS clear for WB type BOs
Date: Wed, 28 Aug 2024 12:31:06 +0300	[thread overview]
Message-ID: <871q29yox1.fsf@intel.com> (raw)
In-Reply-To: <20240827154910.24841-1-nirmoy.das@intel.com>

On Tue, 27 Aug 2024, Nirmoy Das <nirmoy.das@intel.com> wrote:
> HW treats any access to 1-way or 2-way coherent memory as compression
> disabled memory. So for such BOs there is no need to do CCS clearing.
>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_bo.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
> index cbe7bf098970..24701272e3af 100644
> --- a/drivers/gpu/drm/xe/xe_bo.c
> +++ b/drivers/gpu/drm/xe/xe_bo.c
> @@ -283,6 +283,7 @@ struct xe_ttm_tt {
>  	struct device *dev;
>  	struct sg_table sgt;
>  	struct sg_table *sg;
> +	bool skip_ccs_clear:1;

There's no benefit in using a bitfield here, I don't think.

BR,
Jani.

>  };
>  
>  static int xe_tt_map_sg(struct ttm_tt *tt)
> @@ -404,6 +405,8 @@ static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo,
>  	if (ttm_bo->type == ttm_bo_type_device && xe->mem.gpu_page_clear_sys)
>  		page_flags |= TTM_TT_FLAG_CLEARED_ON_FREE;
>  
> +	/* compression is not allowed for cached BO so ccs clear can be skipped. */
> +	tt->skip_ccs_clear = caching == ttm_cached;
>  	err = ttm_tt_init(&tt->ttm, &bo->ttm, page_flags, caching, extra_pages);
>  	if (err) {
>  		kfree(tt);
> @@ -664,13 +667,16 @@ static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict,
>  	struct ttm_resource *old_mem = ttm_bo->resource;
>  	u32 old_mem_type = old_mem ? old_mem->mem_type : XE_PL_SYSTEM;
>  	struct ttm_tt *ttm = ttm_bo->ttm;
> +	struct xe_ttm_tt *xe_tt = container_of(ttm_bo->ttm, struct xe_ttm_tt,
> +					       ttm);
>  	struct xe_migrate *migrate = NULL;
>  	struct dma_fence *fence;
>  	bool move_lacks_source;
>  	bool tt_has_data;
>  	bool needs_clear;
>  	bool handle_system_ccs = (!IS_DGFX(xe) && xe_bo_needs_ccs_pages(bo) &&
> -				  ttm && ttm_tt_is_populated(ttm)) ? true : false;
> +				  ttm && ttm_tt_is_populated(ttm) &&
> +				  !xe_tt->skip_ccs_clear) ? true : false;
>  	bool clear_system_pages;
>  	int ret = 0;

-- 
Jani Nikula, Intel

  parent reply	other threads:[~2024-08-28  9:31 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-27 15:49 [PATCH 1/2] drm/xe: Skip CCS clear for WB type BOs Nirmoy Das
2024-08-27 15:49 ` [PATCH 2/2] Revert "drm/xe/lnl: Offload system clear page activity to GPU" Nirmoy Das
2024-08-27 19:49   ` Matthew Brost
2024-08-28  8:24     ` Nirmoy Das
2024-08-27 16:27 ` ✓ CI.Patch_applied: success for series starting with [1/2] drm/xe: Skip CCS clear for WB type BOs Patchwork
2024-08-27 16:28 ` ✓ CI.checkpatch: " Patchwork
2024-08-27 16:29 ` ✓ CI.KUnit: " Patchwork
2024-08-27 16:41 ` ✓ CI.Build: " Patchwork
2024-08-27 16:43 ` ✓ CI.Hooks: " Patchwork
2024-08-27 16:45 ` ✓ CI.checksparse: " Patchwork
2024-08-27 17:04 ` ✓ CI.BAT: " Patchwork
2024-08-28  1:16 ` ✗ CI.FULL: failure " Patchwork
2024-08-28  8:23 ` [PATCH 1/2] " Thomas Hellström
2024-08-28  8:34   ` Nirmoy Das
2024-08-28  8:36     ` Maarten Lankhorst
2024-08-28  9:31 ` Jani Nikula [this message]
2024-08-28 12:09   ` Nirmoy Das

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