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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>,
	intel-gfx@lists.freedesktop.org
Cc: matthew.d.roper@intel.com, haridhar.kalvala@intel.com,
	Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Subject: Re: [PATCH] drm/i915/display: correct dual pps handling for MTL_PCH+
Date: Thu, 01 Aug 2024 15:25:42 +0300	[thread overview]
Message-ID: <871q38whtl.fsf@intel.com> (raw)
In-Reply-To: <20240801111141.574854-1-dnyaneshwar.bhadane@intel.com>

On Thu, 01 Aug 2024, Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> wrote:
> On the PCH side the second PPS was introduced in ICP+.Add condition
> On MTL_PCH and greater platform also having the second PPS.
>
> Note that DG1/2 south block only has the single PPS, so need
> to exclude the fake DG1/2 PCHs
>
> Link: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11488

Closes:, not Link:

Fixes: 93cbc1accbce ("drm/i915/mtl: Add fake PCH for Meteor Lake")
Cc: <stable@vger.kernel.org> # v6.9+

Can be fixed while applying, no need to resend.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_backlight.c | 3 +++
>  drivers/gpu/drm/i915/display/intel_pps.c       | 3 +++
>  2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
> index 071668bfe5d1..6c3333136737 100644
> --- a/drivers/gpu/drm/i915/display/intel_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_backlight.c
> @@ -1449,6 +1449,9 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
>  
>  static int cnp_num_backlight_controllers(struct drm_i915_private *i915)
>  {
> +	if (INTEL_PCH_TYPE(i915) >= PCH_MTL)
> +		return 2;
> +
>  	if (INTEL_PCH_TYPE(i915) >= PCH_DG1)
>  		return 1;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index 42306bc4ba86..7ce926241e83 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -351,6 +351,9 @@ static int intel_num_pps(struct drm_i915_private *i915)
>  	if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
>  		return 2;
>  
> +	if (INTEL_PCH_TYPE(i915) >= PCH_MTL)
> +		return 2;
> +
>  	if (INTEL_PCH_TYPE(i915) >= PCH_DG1)
>  		return 1;

-- 
Jani Nikula, Intel

  reply	other threads:[~2024-08-01 12:25 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-01 11:11 [PATCH] drm/i915/display: correct dual pps handling for MTL_PCH+ Dnyaneshwar Bhadane
2024-08-01 12:25 ` Jani Nikula [this message]
2024-08-01 13:42 ` ✓ Fi.CI.BAT: success for " Patchwork
2024-08-02  7:14 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-08-26 17:00   ` Matt Roper
2024-08-26 17:01     ` Matt Roper
2024-08-27  9:25       ` Jani Nikula

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