From: Kurt Kanzenbach <kurt@linutronix.de>
To: AKASHI Takahiro <takahiro.akashi@linaro.org>,
jesse.brandeburg@intel.com, anthony.l.nguyen@intel.com
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>,
intel-wired-lan@lists.osuosl.org
Subject: Re: [Intel-wired-lan] [PATCH] igc: fix the validation logic for taprio's gate list
Date: Tue, 07 Mar 2023 11:46:33 +0100 [thread overview]
Message-ID: <871qm0j0ty.fsf@kurt> (raw)
In-Reply-To: <20230307064531.68840-1-takahiro.akashi@linaro.org>
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On Tue Mar 07 2023, AKASHI Takahiro wrote:
> The check introduced in the commit a5fd39464a40 ("igc: Lift TAPRIO schedule
> restriction") can detect a false positive error in some corner case.
> For instance,
> tc qdisc replace ... taprio num_tc 4
> ...
> sched-entry S 0x01 100000 # slot#1
> sched-entry S 0x03 100000 # slot#2
> sched-entry S 0x04 100000 # slot#3
> sched-entry S 0x08 200000 # slot#4
> flags 0x02 # hardware offload
>
> Here the queue#0 (the first queue) is on at the slot#1 and #2,
> and off at the slot#3 and #4. Under the current logic, when the slot#4
> is examined, validate_schedule() returns *false* since the enablement
> count for the queue#0 is two and it is already off at the previous slot
> (i.e. #3). But this definition is truely correct.
>
> Let's fix the logic to enforce a strict validation for consecutively-opened
> slots.
>
> Fixes: a5fd39464a40 ("igc: Lift TAPRIO schedule restriction")
> Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Grml. Thanks!
Reviewed-by: Kurt Kanzenbach <kurt@linutronix.de>
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next prev parent reply other threads:[~2023-03-07 10:54 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-07 6:45 [Intel-wired-lan] [PATCH] igc: fix the validation logic for taprio's gate list AKASHI Takahiro
2023-03-07 10:46 ` Kurt Kanzenbach [this message]
2023-03-08 21:40 ` Vinicius Costa Gomes
2023-03-14 8:44 ` naamax.meir
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