From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alex =?utf-8?Q?Benn=C3=A9e?= Subject: Re: [RFC PATCH 13/16] KVM: Allow 2048-bit register access via KVM_{GET, SET}_ONE_REG Date: Thu, 26 Jul 2018 14:55:44 +0100 Message-ID: <871sbqt82n.fsf@linaro.org> References: <1529593060-542-1-git-send-email-Dave.Martin@arm.com> <1529593060-542-14-git-send-email-Dave.Martin@arm.com> <874lgntihl.fsf@linaro.org> <20180726125834.GV4240@e103592.cambridge.arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id C71254043C for ; Thu, 26 Jul 2018 09:55:47 -0400 (EDT) Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2N2j08-2yKG6 for ; Thu, 26 Jul 2018 09:55:46 -0400 (EDT) Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id B778740217 for ; Thu, 26 Jul 2018 09:55:46 -0400 (EDT) Received: by mail-wr1-f65.google.com with SMTP id h9-v6so1825771wro.3 for ; Thu, 26 Jul 2018 06:55:46 -0700 (PDT) In-reply-to: <20180726125834.GV4240@e103592.cambridge.arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu To: Dave Martin Cc: Okamoto Takayuki , Christoffer Dall , Ard Biesheuvel , Marc Zyngier , Catalin Marinas , Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org List-Id: kvmarm@lists.cs.columbia.edu CkRhdmUgTWFydGluIDxEYXZlLk1hcnRpbkBhcm0uY29tPiB3cml0ZXM6Cgo+IE9uIFdlZCwgSnVs IDI1LCAyMDE4IGF0IDA0OjU4OjMwUE0gKzAxMDAsIEFsZXggQmVubsOpZSB3cm90ZToKPj4KPj4g RGF2ZSBNYXJ0aW4gPERhdmUuTWFydGluQGFybS5jb20+IHdyaXRlczoKPj4KPj4gPiBUaGUgQXJt IFNWRSBhcmNoaXRlY3R1cmUgZGVmaW5lcyByZWdpc3RlcnMgdGhhdCBhcmUgdXAgdG8gMjA0OCBi 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IHNldCBhcwp1bmxlc3MgeW91IHNwZWNpZnkgb3RoZXJ3aXNlIHdlIHVzZSB0aGUgcmVzdWx0cyBv ZiBwcm9iZWQ6CgogIHJldCA9IGlvY3RsKHZtZmQsIEtWTV9BUk1fUFJFRkVSUkVEX1RBUkdFVCwg aW5pdCk7CgpzbyB0aGUgdXNlciB3aWxsIGdldCBpdCBieSBkZWZpbml0aW9uIHdoZW4gdGhleSBm aXJzdCBydW4gb24gU1ZFIGNhcGFibGUKaGFyZHdhcmUuCgoKPgo+IENoZWVycwo+IC0tLURhdmUK CgotLQpBbGV4IEJlbm7DqWUKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX18Ka3ZtYXJtIG1haWxpbmcgbGlzdAprdm1hcm1AbGlzdHMuY3MuY29sdW1iaWEuZWR1 Cmh0dHBzOi8vbGlzdHMuY3MuY29sdW1iaWEuZWR1L21haWxtYW4vbGlzdGluZm8va3ZtYXJtCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: alex.bennee@linaro.org (Alex =?utf-8?Q?Benn=C3=A9e?=) Date: Thu, 26 Jul 2018 14:55:44 +0100 Subject: [RFC PATCH 13/16] KVM: Allow 2048-bit register access via KVM_{GET, SET}_ONE_REG In-Reply-To: <20180726125834.GV4240@e103592.cambridge.arm.com> References: <1529593060-542-1-git-send-email-Dave.Martin@arm.com> <1529593060-542-14-git-send-email-Dave.Martin@arm.com> <874lgntihl.fsf@linaro.org> <20180726125834.GV4240@e103592.cambridge.arm.com> Message-ID: <871sbqt82n.fsf@linaro.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Dave Martin writes: > On Wed, Jul 25, 2018 at 04:58:30PM +0100, Alex Benn?e wrote: >> >> Dave Martin writes: >> >> > The Arm SVE architecture defines registers that are up to 2048 bits >> > in size (with some possibility of further future expansion). >> > >> > In order to avoid the need for an excessively large number of >> > ioctls when saving and restoring a vcpu's registers, this patch >> > adds a #define to make support for individual 2048-bit registers >> > through the KVM_{GET,SET}_ONE_REG ioctl interface official. This >> > will allow each SVE register to be accessed in a single call. >> > >> > There are sufficient spare bits in the register id size field for >> > this change, so there is no ABI impact providing that >> > KVM_GET_REG_LIST does not enumerate any 2048-bit register unless >> > userspace explicitly opts in to the relevant architecture-specific >> > features. >> >> Does it? It's not in this patch and looking at the final tree: >> >> unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu) >> { >> unsigned long res = 0; >> >> res += num_core_regs(); >> res += num_sve_regs(vcpu); >> res += kvm_arm_num_sys_reg_descs(vcpu); >> res += kvm_arm_get_fw_num_regs(vcpu); >> res += NUM_TIMER_REGS; >> >> return res; >> } >> >> >> which leads to: >> >> static int enumerate_sve_regs(const struct kvm_vcpu *vcpu, u64 __user **uind) >> { >> unsigned int n, i; >> int err = 0; >> int total = 0; >> unsigned int slices; >> >> if (!vcpu_has_sve(&vcpu->arch)) >> return 0; >> >> Which enumerates the SVE regs if vcpu_has_sve() which AFAICT is true if >> the host supports it, not if the user has requested it. >> >> I'll have to check what but given the indirection of kvm_one_reg I >> wonder if existing binaries might end up spamming a badly sized array >> when run on a new SVE supporting kernel? > > That shouldn't be the case: vcpu_has_sve() checks for the > KVM_ARM64_GUEST_HAS_SVE flag, which should only be set if userspace asks > for it. > > Give me a shout if this doesn't seem to be the case... Ahh I missed it the first time: if (system_supports_sve() && test_bit(KVM_ARM_VCPU_SVE, vcpu->arch.features)) { vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_SVE; And vcpu->arch.features is set by the user. However it will be set as unless you specify otherwise we use the results of probed: ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, init); so the user will get it by definition when they first run on SVE capable hardware. > > Cheers > ---Dave -- Alex Benn?e