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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/3] drm/i915/execlists: Reset ring registers on rebinding contexts
Date: Wed, 28 Mar 2018 14:31:33 +0300	[thread overview]
Message-ID: <871sg44esq.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20180327210157.16896-1-chris@chris-wilson.co.uk>

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Tvrtko uncovered a fun issue with recovering from a wedge device. In his
> tests, he wedged the driver by injecting an unrecoverable hang whilst a
> batch was spinning. As we reset the gpu in the middle of the spinner,
> when resumed it would continue on from the next instruction in the ring
> and write it's breadcrumb. However, on wedging we updated our
> bookkeeping to indicate that the GPU had completed executing and would
> restart from after the breadcrumb; so the emission of the stale
> breadcrumb from before the reset came as a bit of a surprise.
>
> A simple fix is to when rebinding the context into the GPU, we update
> the ring register state in the context image to match our bookkeeping.
> We already have to update the RING_START and RING_TAIL, so updating
> RING_HEAD as well is trivial. This works because whenever we unbind the
> context, we keep the bookkeeping in check; and on wedging we unbind all
> contexts.

s/wedging/unwedging. The context lost markup is on unwedge side tho
it should not matter on which stage the unbind happends between
wedge and unwedge so this minor change to commit message and

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

>
> Testcase: igt/gem_eio
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index ba7f7831f934..654634254b64 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1272,6 +1272,7 @@ execlists_context_pin(struct intel_engine_cs *engine,
>  	ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
>  	ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
>  		i915_ggtt_offset(ce->ring->vma);
> +	ce->lrc_reg_state[CTX_RING_HEAD+1] = ce->ring->head;
>  
>  	ce->state->obj->pin_global++;
>  	i915_gem_context_get(ctx);
> -- 
> 2.16.3
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      parent reply	other threads:[~2018-03-28 11:31 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-27 21:01 [PATCH 1/3] drm/i915/execlists: Reset ring registers on rebinding contexts Chris Wilson
2018-03-27 21:01 ` [PATCH 2/3] drm/i915/execlists: Delay updating ring register state after resume Chris Wilson
2018-03-27 23:05   ` Chris Wilson
2018-03-27 23:10   ` [PATCH v2] " Chris Wilson
2018-03-28 13:40     ` Mika Kuoppala
2018-03-27 21:01 ` [PATCH 3/3] drm/i915: Include the HW breadcrumb whenever we trace the global_seqno Chris Wilson
2018-03-29  8:42   ` Tvrtko Ursulin
2018-03-29  8:55     ` Chris Wilson
2018-03-29  9:43       ` Tvrtko Ursulin
2018-03-29 11:22         ` Chris Wilson
2018-03-27 22:38 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/execlists: Reset ring registers on rebinding contexts Patchwork
2018-03-27 22:53 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-03-27 23:58 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/execlists: Reset ring registers on rebinding contexts (rev2) Patchwork
2018-03-28  0:13 ` ✓ Fi.CI.BAT: success " Patchwork
2018-03-28 10:12 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-03-28 11:31 ` Mika Kuoppala [this message]

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