From: Jani Nikula <jani.nikula@intel.com>
To: "Chauhan, Madhav" <madhav.chauhan@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Cc: "Conselvan De Oliveira,
Ander" <ander.conselvan.de.oliveira@intel.com>,
"Deepak, M" <m.deepak@intel.com>,
"Kumar, Shobhit" <shobhit.kumar@intel.com>
Subject: Re: [GLK MIPI DSI V1 1/9] drm/i915/glk: Add new bit fields in MIPI CTRL register
Date: Wed, 14 Dec 2016 13:46:44 +0200 [thread overview]
Message-ID: <871sxaspgb.fsf@intel.com> (raw)
In-Reply-To: <FDE0F82259988449BC0C053E4EF090C947FB0980@BGSMSX104.gar.corp.intel.com>
On Wed, 14 Dec 2016, "Chauhan, Madhav" <madhav.chauhan@intel.com> wrote:
> Overall, any bit field/register (added in this series) specific to GLK
> should have GLK_ and common to GLK/BXT should have GEN9LP_ ??
It's a long standing convention in the driver to name things after the
first platform they were introduced in.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
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next prev parent reply other threads:[~2016-12-14 11:46 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-08 8:49 [GLK MIPI DSI V1 0/9] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
2016-12-08 8:49 ` [GLK MIPI DSI V1 1/9] drm/i915/glk: Add new bit fields in MIPI CTRL register Madhav Chauhan
2016-12-13 11:36 ` Jani Nikula
2016-12-14 11:02 ` Chauhan, Madhav
2016-12-14 11:46 ` Jani Nikula [this message]
2016-12-14 12:20 ` Chauhan, Madhav
2016-12-08 8:49 ` [GLK MIPI DSI V1 2/9] drm/i915/glk: Program new MIPI DSI PHY registers for GLK Madhav Chauhan
2016-12-08 8:49 ` [GLK MIPI DSI V1 3/9] drm/i915/glk: Add MIPIIO Enable/disable sequence Madhav Chauhan
2016-12-08 8:49 ` [GLK MIPI DSI V1 4/9] drm/i915: Set the Z inversion overlap field Madhav Chauhan
2016-12-08 8:49 ` [GLK MIPI DSI V1 5/9] drm/i915/glk: Add DSI PLL divider range for glk Madhav Chauhan
2016-12-08 8:50 ` [GLK MIPI DSI V1 6/9] drm/i915/glk: Program MIPI_CLOCK_CTRL only for BXT Madhav Chauhan
2016-12-08 8:50 ` [GLK MIPI DSI V1 7/9] drm/i915/glk: Program txesc clock divider for GLK Madhav Chauhan
2016-12-08 8:50 ` [GLK MIPI DSI V1 8/9] drm/i915/glk: Program dphy param reg " Madhav Chauhan
2016-12-08 8:50 ` [GLK MIPI DSI V1 9/9] drm/915: Parsing the missed out DTD fields from the VBT Madhav Chauhan
2016-12-08 9:22 ` ✓ Fi.CI.BAT: success for GLK MIPI DSI VIDEO MODE PATCHES Patchwork
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