diff for duplicates of <871sxhf48h.fsf@free-electrons.com> diff --git a/a/1.txt b/N1/1.txt index cde2b46..c0b54f6 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,19 +1,17 @@ Hi Russell King, -=20 - On jeu., d=C3=A9c. 08 2016, Russell King - ARM Linux <linux@armlinux.org.u= -k> wrote: + + On jeu., d?c. 08 2016, Russell King - ARM Linux <linux@armlinux.org.uk> wrote: > On Thu, Dec 08, 2016 at 06:10:08PM +0100, Gregory CLEMENT wrote: >> From: Shaker Daibes <shaker@marvell.com> ->>=20 +>> >> According to FE-3124064: >> The device supports CPU write and read access to the RTC time register. >> However, due to this errata, read from RTC TIME register may fail. ->>=20 +>> >> Workaround: >> General configuration: ->> 1. Configure the RTC Mbus Bridge Timing Control register (offset 0x184A0= -) +>> 1. Configure the RTC Mbus Bridge Timing Control register (offset 0x184A0) >> to value 0xFD4D4FFF >> Write RTC WRCLK Period to its maximum value (0x3FF) >> Write RTC WRCLK setup to 0x53 (default value ) @@ -22,18 +20,18 @@ k> wrote: >> Mbus - Read All Byte Enable to 0x1 (default value ) >> 2. Configure the RTC Test Configuration Register (offset 0xA381C) bit3 >> to '1' (Reserved, Marvell internal) ->>=20 +>> >> For any RTC register read operation: >> 1. Read the requested register 100 times. >> 2. Find the result that appears most frequently and use this result >> as the correct value. ->>=20 +>> >> For any RTC register write operation: >> 1. Issue two dummy writes of 0x0 to the RTC Status register (offset >> 0xA3800). >> 2. Write the time to the RTC Time register (offset 0xA380C). ->>=20 ->> [gregory.clement@free-electrons.com: cosmetic changes and fix issues for +>> +>> [gregory.clement at free-electrons.com: cosmetic changes and fix issues for >> interrupt in original patch] > > A particularly interesting question here is whether the above description @@ -42,7 +40,7 @@ k> wrote: Well, it is difficult to say. the above description comes from the errata datasheet (since rev B). But the errata sheet itself mentioned -the software implementation in one of the Marvell release.=20 +the software implementation in one of the Marvell release. > @@ -53,14 +51,13 @@ the software implementation in one of the Marvell release.=20 Do you suggest to use the the relaxed version of readl() and writel()? > ->>=20 +>> >> Reviewed-by: Lior Amsalem <alior@marvell.com> >> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> >> --- ->> drivers/rtc/rtc-armada38x.c | 109 ++++++++++++++++++++++++++++++++++---= -------- +>> drivers/rtc/rtc-armada38x.c | 109 ++++++++++++++++++++++++++++++++++---------- >> 1 file changed, 85 insertions(+), 24 deletions(-) ->>=20 +>> >> diff --git a/drivers/rtc/rtc-armada38x.c b/drivers/rtc/rtc-armada38x.c >> index 9a3f2a6f512e..a0859286a4c4 100644 >> --- a/drivers/rtc/rtc-armada38x.c @@ -68,7 +65,7 @@ Do you suggest to use the the relaxed version of readl() and writel()? >> @@ -29,12 +29,21 @@ >> #define RTC_TIME 0xC >> #define RTC_ALARM1 0x10 ->> =20 +>> >> +#define SOC_RTC_BRIDGE_TIMING_CTL 0x0 >> +#define SOC_RTC_PERIOD_OFFS 0 >> +#define SOC_RTC_PERIOD_MASK (0x3FF << SOC_RTC_PERIOD_OFFS) @@ -80,7 +77,7 @@ Do you suggest to use the the relaxed version of readl() and writel()? >> #define SOC_RTC_ALARM2 BIT(1) >> #define SOC_RTC_ALARM1_MASK BIT(2) >> #define SOC_RTC_ALARM2_MASK BIT(3) ->> =20 +>> >> + >> +#define SAMPLE_NR 100 >> + @@ -97,25 +94,24 @@ Do you suggest to use the the relaxed version of readl() and writel()? >> + * register. >> */ >> + ->> static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int o= -ffset) +>> static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset) >> { >> + writel(0, rtc->regs + RTC_STATUS); >> + writel(0, rtc->regs + RTC_STATUS); >> writel(val, rtc->regs + offset); >> udelay(5); >> } ->> =20 +>> >> +/* Update RTC-MBUS bridge timing parameters */ >> +static void rtc_update_mbus_timing_params(struct armada38x_rtc *rtc) >> +{ >> + uint32_t reg; >> + ->> + reg =3D readl(rtc->regs_soc + SOC_RTC_BRIDGE_TIMING_CTL); ->> + reg &=3D ~SOC_RTC_PERIOD_MASK; ->> + reg |=3D 0x3FF << SOC_RTC_PERIOD_OFFS; /* Maximum value */ ->> + reg &=3D ~SOC_RTC_READ_DELAY_MASK; ->> + reg |=3D 0x1F << SOC_RTC_READ_DELAY_OFFS; /* Maximum value */ +>> + reg = readl(rtc->regs_soc + SOC_RTC_BRIDGE_TIMING_CTL); +>> + reg &= ~SOC_RTC_PERIOD_MASK; +>> + reg |= 0x3FF << SOC_RTC_PERIOD_OFFS; /* Maximum value */ +>> + reg &= ~SOC_RTC_READ_DELAY_MASK; +>> + reg |= 0x1F << SOC_RTC_READ_DELAY_OFFS; /* Maximum value */ >> + writel(reg, rtc->regs_soc + SOC_RTC_BRIDGE_TIMING_CTL); >> +} >> + @@ -134,20 +130,8 @@ Thanks, Gregory ---=20 +-- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com - ---=20 -You received this message because you are subscribed to "rtc-linux". -Membership options at http://groups.google.com/group/rtc-linux . -Please read http://groups.google.com/group/rtc-linux/web/checklist -before submitting a driver. ----=20 -You received this message because you are subscribed to the Google Groups "= -rtc-linux" group. -To unsubscribe from this group and stop receiving emails from it, send an e= -mail to rtc-linux+unsubscribe@googlegroups.com. -For more options, visit https://groups.google.com/d/optout. diff --git a/a/content_digest b/N1/content_digest index 575f2e1..9250a22 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,37 +1,26 @@ "ref\020161208171010.29446-1-gregory.clement@free-electrons.com\0" "ref\020161208171010.29446-2-gregory.clement@free-electrons.com\0" "ref\020161208173717.GJ14217@n2100.armlinux.org.uk\0" - "From\0Gregory CLEMENT <gregory.clement@free-electrons.com>\0" - "Subject\0[rtc-linux] Re: [PATCH 1/3] rtc: armada38x: improve RTC errata implementation\0" + "From\0gregory.clement@free-electrons.com (Gregory CLEMENT)\0" + "Subject\0[PATCH 1/3] rtc: armada38x: improve RTC errata implementation\0" "Date\0Fri, 09 Dec 2016 17:37:34 +0100\0" - "To\0Russell King - ARM Linux <linux@armlinux.org.uk>\0" - "Cc\0Alessandro Zummo <a.zummo@towertech.it>" - Alexandre Belloni <alexandre.belloni@free-electrons.com> - rtc-linux@googlegroups.com - Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - Andrew Lunn <andrew@lunn.ch> - Jason Cooper <jason@lakedaemon.net> - Shaker Daibes <shaker@marvell.com> - linux-arm-kernel@lists.infradead.org - " Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi Russell King,\n" - "=20\n" - " On jeu., d=C3=A9c. 08 2016, Russell King - ARM Linux <linux@armlinux.org.u=\n" - "k> wrote:\n" + " \n" + " On jeu., d?c. 08 2016, Russell King - ARM Linux <linux@armlinux.org.uk> wrote:\n" "\n" "> On Thu, Dec 08, 2016 at 06:10:08PM +0100, Gregory CLEMENT wrote:\n" ">> From: Shaker Daibes <shaker@marvell.com>\n" - ">>=20\n" + ">> \n" ">> According to FE-3124064:\n" ">> The device supports CPU write and read access to the RTC time register.\n" ">> However, due to this errata, read from RTC TIME register may fail.\n" - ">>=20\n" + ">> \n" ">> Workaround:\n" ">> General configuration:\n" - ">> 1. Configure the RTC Mbus Bridge Timing Control register (offset 0x184A0=\n" - ")\n" + ">> 1. Configure the RTC Mbus Bridge Timing Control register (offset 0x184A0)\n" ">> to value 0xFD4D4FFF\n" ">> Write RTC WRCLK Period to its maximum value (0x3FF)\n" ">> Write RTC WRCLK setup to 0x53 (default value )\n" @@ -40,18 +29,18 @@ ">> Mbus - Read All Byte Enable to 0x1 (default value )\n" ">> 2. Configure the RTC Test Configuration Register (offset 0xA381C) bit3\n" ">> to '1' (Reserved, Marvell internal)\n" - ">>=20\n" + ">> \n" ">> For any RTC register read operation:\n" ">> 1. Read the requested register 100 times.\n" ">> 2. Find the result that appears most frequently and use this result\n" ">> as the correct value.\n" - ">>=20\n" + ">> \n" ">> For any RTC register write operation:\n" ">> 1. Issue two dummy writes of 0x0 to the RTC Status register (offset\n" ">> 0xA3800).\n" ">> 2. Write the time to the RTC Time register (offset 0xA380C).\n" - ">>=20\n" - ">> [gregory.clement@free-electrons.com: cosmetic changes and fix issues for\n" + ">> \n" + ">> [gregory.clement at free-electrons.com: cosmetic changes and fix issues for\n" ">> interrupt in original patch]\n" ">\n" "> A particularly interesting question here is whether the above description\n" @@ -60,7 +49,7 @@ "\n" "Well, it is difficult to say. the above description comes from the\n" "errata datasheet (since rev B). But the errata sheet itself mentioned\n" - "the software implementation in one of the Marvell release.=20\n" + "the software implementation in one of the Marvell release. \n" "\n" "\n" ">\n" @@ -71,14 +60,13 @@ "Do you suggest to use the the relaxed version of readl() and writel()?\n" "\n" ">\n" - ">>=20\n" + ">> \n" ">> Reviewed-by: Lior Amsalem <alior@marvell.com>\n" ">> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>\n" ">> ---\n" - ">> drivers/rtc/rtc-armada38x.c | 109 ++++++++++++++++++++++++++++++++++---=\n" - "-------\n" + ">> drivers/rtc/rtc-armada38x.c | 109 ++++++++++++++++++++++++++++++++++----------\n" ">> 1 file changed, 85 insertions(+), 24 deletions(-)\n" - ">>=20\n" + ">> \n" ">> diff --git a/drivers/rtc/rtc-armada38x.c b/drivers/rtc/rtc-armada38x.c\n" ">> index 9a3f2a6f512e..a0859286a4c4 100644\n" ">> --- a/drivers/rtc/rtc-armada38x.c\n" @@ -86,7 +74,7 @@ ">> @@ -29,12 +29,21 @@\n" ">> #define RTC_TIME\t 0xC\n" ">> #define RTC_ALARM1\t 0x10\n" - ">> =20\n" + ">> \n" ">> +#define SOC_RTC_BRIDGE_TIMING_CTL 0x0\n" ">> +#define SOC_RTC_PERIOD_OFFS\t\t0\n" ">> +#define SOC_RTC_PERIOD_MASK\t\t(0x3FF << SOC_RTC_PERIOD_OFFS)\n" @@ -98,7 +86,7 @@ ">> #define SOC_RTC_ALARM2\t\tBIT(1)\n" ">> #define SOC_RTC_ALARM1_MASK\tBIT(2)\n" ">> #define SOC_RTC_ALARM2_MASK\tBIT(3)\n" - ">> =20\n" + ">> \n" ">> +\n" ">> +#define SAMPLE_NR 100\n" ">> +\n" @@ -115,25 +103,24 @@ ">> + * register.\n" ">> */\n" ">> +\n" - ">> static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int o=\n" - "ffset)\n" + ">> static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset)\n" ">> {\n" ">> +\twritel(0, rtc->regs + RTC_STATUS);\n" ">> +\twritel(0, rtc->regs + RTC_STATUS);\n" ">> \twritel(val, rtc->regs + offset);\n" ">> \tudelay(5);\n" ">> }\n" - ">> =20\n" + ">> \n" ">> +/* Update RTC-MBUS bridge timing parameters */\n" ">> +static void rtc_update_mbus_timing_params(struct armada38x_rtc *rtc)\n" ">> +{\n" ">> +\tuint32_t reg;\n" ">> +\n" - ">> +\treg =3D readl(rtc->regs_soc + SOC_RTC_BRIDGE_TIMING_CTL);\n" - ">> +\treg &=3D ~SOC_RTC_PERIOD_MASK;\n" - ">> +\treg |=3D 0x3FF << SOC_RTC_PERIOD_OFFS; /* Maximum value */\n" - ">> +\treg &=3D ~SOC_RTC_READ_DELAY_MASK;\n" - ">> +\treg |=3D 0x1F << SOC_RTC_READ_DELAY_OFFS; /* Maximum value */\n" + ">> +\treg = readl(rtc->regs_soc + SOC_RTC_BRIDGE_TIMING_CTL);\n" + ">> +\treg &= ~SOC_RTC_PERIOD_MASK;\n" + ">> +\treg |= 0x3FF << SOC_RTC_PERIOD_OFFS; /* Maximum value */\n" + ">> +\treg &= ~SOC_RTC_READ_DELAY_MASK;\n" + ">> +\treg |= 0x1F << SOC_RTC_READ_DELAY_OFFS; /* Maximum value */\n" ">> +\twritel(reg, rtc->regs_soc + SOC_RTC_BRIDGE_TIMING_CTL);\n" ">> +}\n" ">> +\n" @@ -152,22 +139,10 @@ "\n" "Gregory\n" "\n" - "--=20\n" + "-- \n" "Gregory Clement, Free Electrons\n" "Kernel, drivers, real-time and embedded Linux\n" "development, consulting, training and support.\n" - "http://free-electrons.com\n" - "\n" - "--=20\n" - "You received this message because you are subscribed to \"rtc-linux\".\n" - "Membership options at http://groups.google.com/group/rtc-linux .\n" - "Please read http://groups.google.com/group/rtc-linux/web/checklist\n" - "before submitting a driver.\n" - "---=20\n" - "You received this message because you are subscribed to the Google Groups \"=\n" - "rtc-linux\" group.\n" - "To unsubscribe from this group and stop receiving emails from it, send an e=\n" - "mail to rtc-linux+unsubscribe@googlegroups.com.\n" - For more options, visit https://groups.google.com/d/optout. + http://free-electrons.com -7ac93528631f522ca4cc28f25fe5f175ddbf8e87b28b7ad875e3f2a4251d29b4 +5233197d47641843e6176b58514e2f35f0f9effff47aa8ebbe390523b69772bb
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