From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Sanchez, AdolfoX" <adolfox.sanchez@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: force DP lane count on Broadwell platform
Date: Thu, 19 May 2016 09:31:01 +0300 [thread overview]
Message-ID: <871t4yftju.fsf@intel.com> (raw)
In-Reply-To: <56B36C37A8AFDD43BD486A5FC41A6D991E228CD0@CRSMSX101.amr.corp.intel.com>
On Wed, 18 May 2016, "Sanchez, AdolfoX" <adolfox.sanchez@intel.com> wrote:
> A customer of mine decided to work with a modified DP port with only
> two lanes and is facing issues. I guess modifying the suggested
> values might be useful at O.S leve, however I was wondering if
> modifyint the register that I mentioned earlier in the VBIOS would
> accomplish the same for the pre-OS stage.
For the most part, the pre-OS stage is a black box to me. So I don't
really know. But if I had to guess, not a chance. DP just isn't that
simple.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
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prev parent reply other threads:[~2016-05-19 6:31 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-18 0:08 force DP lane count on Broadwell platform Sanchez, AdolfoX
2016-05-18 6:37 ` Jani Nikula
2016-05-18 19:21 ` Sanchez, AdolfoX
2016-05-19 6:31 ` Jani Nikula [this message]
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