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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 12/16] drm/i915/bxt: Sanitize the DBUF HW state	together with CDCLK
Date: Mon, 11 Apr 2016 16:19:53 +0300	[thread overview]
Message-ID: <871t6cp9ja.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <1459515767-29228-13-git-send-email-imre.deak@intel.com>

Imre Deak <imre.deak@intel.com> writes:

> [ text/plain ]
> When determining whether CDCLK is enabled by BIOS and so we should skip
> reprogramming it, we didn't check the related DBUF power request and
> state. In theory BIOS could enable one without the other so check for
> this case and reprogram things if something is amiss.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 28 ++++++++++++++++++++++++++--
>  1 file changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 1fbe619..447d46e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5440,14 +5440,38 @@ static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency)
>  	intel_update_cdclk(dev_priv->dev);
>  }
>  
> +static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
> +{
> +	if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
> +		return false;
> +
> +	/* TODO: Check for a valid CDCLK rate */
> +

Discussed about the pll lock in irc with Imre. I think pll lock bit
should be included in the sanity inspection here too.

But that can be follow ups.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>


> +	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) {
> +		DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
> +
> +		return false;
> +	}
> +
> +	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) {
> +		DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
> +
> +		return false;
> +	}
> +
> +	return true;
> +}
> +
>  void broxton_init_cdclk(struct drm_i915_private *dev_priv)
>  {
>  	/* check if cd clock is enabled */
> -	if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
> -		DRM_DEBUG_KMS("Display already initialized\n");
> +	if (broxton_cdclk_is_enabled(dev_priv)) {
> +		DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");
>  		return;
>  	}
>  
> +	DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
> +
>  	/*
>  	 * FIXME:
>  	 * - The initial CDCLK needs to be read from VBT.
> -- 
> 2.5.0
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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  reply	other threads:[~2016-04-11 13:22 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-01 13:02 [PATCH 00/16] drm/i915/bxt: Fix/enable display power well support/runtime PM Imre Deak
2016-04-01 13:02 ` [PATCH 01/16] drm/i915/bxt: Reject DMC firmware versions with known bugs Imre Deak
2016-04-11 12:39   ` Mika Kuoppala
2016-04-01 13:02 ` [PATCH 02/16] drm/i915/bxt: Fix GRC code register field definitions Imre Deak
2016-04-08 17:22   ` Ville Syrjälä
2016-04-08 17:27     ` Imre Deak
2016-04-01 13:02 ` [PATCH 03/16] drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-only Imre Deak
2016-04-08 18:02   ` Ville Syrjälä
2016-04-08 18:12     ` Imre Deak
2016-04-08 18:16       ` Imre Deak
2016-04-12 15:11   ` David Weinehall
2016-04-01 13:02 ` [PATCH 04/16] drm/i915/bxt: Reset secondary power well requests left on by DMC/KVMR Imre Deak
2016-04-05 10:26   ` [PATCH v2 04/16] drm/i915/gen9: " Imre Deak
2016-04-06 10:59     ` Patrik Jakobsson
2016-04-01 13:02 ` [PATCH 05/16] drm/i915/gen9: Make power well disabling synchronous Imre Deak
2016-04-04 10:34   ` Patrik Jakobsson
2016-04-05  8:26     ` Patrik Jakobsson
2016-04-05  9:30       ` Imre Deak
2016-04-01 13:02 ` [PATCH 06/16] drm/i915/gen9: Fix DMC/DC state asserts Imre Deak
2016-04-04 10:52   ` Patrik Jakobsson
2016-04-01 13:02 ` [PATCH 07/16] drm/i915/bxt: Suspend power domains during suspend-to-idle Imre Deak
2016-04-04 11:28   ` Patrik Jakobsson
2016-04-01 13:02 ` [PATCH 08/16] drm/i915/skl: Unexport skl_pw1_misc_io_init Imre Deak
2016-04-04 12:30   ` Patrik Jakobsson
2016-04-04 12:34     ` Imre Deak
2016-04-04 12:42   ` [PATCH v2 " Imre Deak
2016-04-04 13:01     ` Patrik Jakobsson
2016-04-04 13:54       ` Imre Deak
2016-04-01 13:02 ` [PATCH 09/16] drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpers Imre Deak
2016-04-08 18:03   ` Ville Syrjälä
2016-04-12 15:12   ` David Weinehall
2016-04-01 13:02 ` [PATCH 10/16] drm/i915/bxt: Power down DDI PHYs separately during the per PHY uninit Imre Deak
2016-04-01 13:29   ` Jani Nikula
2016-04-01 13:40     ` Imre Deak
2016-04-08 18:04   ` Ville Syrjälä
2016-04-01 13:02 ` [PATCH 11/16] drm/i915/bxt: Don't toggle power well 1 on-demand Imre Deak
2016-04-08 18:10   ` Ville Syrjälä
2016-04-01 13:02 ` [PATCH 12/16] drm/i915/bxt: Sanitize the DBUF HW state together with CDCLK Imre Deak
2016-04-11 13:19   ` Mika Kuoppala [this message]
2016-04-01 13:02 ` [PATCH 13/16] drm/i915/bxt: Don't reprogram an already enabled DDI PHY Imre Deak
2016-04-08 18:15   ` Ville Syrjälä
2016-04-01 13:02 ` [PATCH 14/16] drm/i915/bxt: Add HW state verification for DDI PHY and CDCLK Imre Deak
2016-04-01 14:28   ` [PATCH v2 " Imre Deak
2016-04-04 14:27     ` [PATCH v3 " Imre Deak
2016-04-12 15:21       ` David Weinehall
2016-04-01 13:02 ` [PATCH 15/16] Revert "drm/i915/bxt: Disable power well support" Imre Deak
2016-04-12 15:22   ` David Weinehall
2016-04-01 13:02 ` [PATCH 16/16] drm/i915/bxt: Enable runtime PM Imre Deak
2016-04-12 15:21   ` David Weinehall
2016-04-01 13:45 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: Fix/enable display power well support/runtime PM Patchwork
2016-04-01 14:35 ` ✓ Fi.CI.BAT: success for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev2) Patchwork
2016-04-04 14:07 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev3) Patchwork
2016-04-04 15:56 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev4) Patchwork
2016-04-05 12:19 ` ✓ Fi.CI.BAT: success for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev5) Patchwork
2016-04-15 12:06   ` Imre Deak

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