Re: using perfctr to determine cache miss rate

[Ed L Cashin <ecashin@uga.edu>]

"David S. Miller" <davem@redhat.com> writes:

> On Fri, 20 Feb 2004 22:23:47 -0500
> Ed L Cashin <ecashin@uga.edu> wrote:
>
>> Is there a way to measure the number of memory accesses (both reads
>> and writes) that are not hitting in any cache?  It appears not to be
>> possible, since only two events can be observed at once, and the
>> events are quite specific (e.g. observing dcache write hits makes
>> dcache read hits unobservable).
>
> That's right, this is one of the limitations, since you only sample
> two events there are certain things you can't sample in one go.
> You could run multiple times, sampling different events each time,
> but the results won't be so accurate.

My advisor pointed out that if any level one miss will result in an
ecache reference, then counting ecache references and subtracting
ecache hits will measure "cache misses" accurately.

That seems right to me.  Is there some problem with that strategy?

-- 
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