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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: VE1PR03MB6078.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4e5b101d-c4e2-456f-c2b8-08df19051b0c X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Sep 2026 23:56:22.9048 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: MRPBds/5d0BRuLI+s/FbKqd+3SwIu9436CR0LtkQ/XhpxFpQhX2IGfz86CfyAodXKSjeB47sErcX68jPvoYZcmN+KVlAIjycp4R5gZZ/f8s= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BESPR03MB11843 X-purgate-ID: tlsNG-4011c0/1790121386-51CC3CFC-46DFCBA0/0/0 X-purgate-type: clean X-purgate-size: 3932 Hi Mykola, Mykola Kvach writes: > The boot CPU pending table must use the memory attributes selected by > ITS quirks. gicv3_lpi_init_host_lpis() is therefore called after > gicv3_its_init(). However, gicv3_its_init() also programs and enables > each ITS before host LPI state is allocated. No ITS commands are > submitted at that point, but this ordering relies on that implementation > detail. > > Split per-ITS initialization into preparation and activation phases. > First map and disable every ITS and collect its quirks. Then initialize > host LPI state. Only after that, allocate and program the ITS tables and > command queue, and enable each ITS. > > The subsequent gicv3_cpu_init() sequence remains unchanged: it programs > the Redistributor LPI tables, enables LPIs, and then submits the first > MAPC and SYNC commands. > > Suggested-by: Julien Grall > Signed-off-by: Mykola Kvach > --- > Changes in v3: > - New patch implementing the post-4.22 initialization order discussed > during review of the ordering fix. > > Link: https://patchew.org/Xen/341edd8de63dcd84ccc6e7b6c03e9e8fc7105184.17= 81847061.git.mykola._5Fkvach@epam.com/ > --- > xen/arch/arm/gic-v3-its.c | 32 ++++++++++++++++++++++----- > xen/arch/arm/gic-v3.c | 15 ++----------- > xen/arch/arm/include/asm/gic_v3_its.h | 4 ++-- > 3 files changed, 31 insertions(+), 20 deletions(-) > > diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c > index 325835b0ad..972825bf06 100644 > --- a/xen/arch/arm/gic-v3-its.c > +++ b/xen/arch/arm/gic-v3-its.c > @@ -11,6 +11,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -549,10 +550,9 @@ static int gicv3_disable_its(struct host_its *hw_its= ) > return -ETIMEDOUT; > } > =20 > -static int gicv3_its_init_single_its(struct host_its *hw_its) > +static int __init gicv3_its_prepare_single_its(struct host_its *hw_its) > { > - uint64_t reg; > - int i, ret; > + int ret; > =20 > hw_its->its_base =3D ioremap_nocache(hw_its->addr, hw_its->size); > if ( !hw_its->its_base ) > @@ -564,6 +564,14 @@ static int gicv3_its_init_single_its(struct host_its= *hw_its) > =20 > gicv3_its_enable_quirks(hw_its); > =20 > + return 0; > +} > + > +static int __init gicv3_its_init_single_its(struct host_its *hw_its) > +{ > + uint64_t reg; > + int i, ret; > + > reg =3D readq_relaxed(hw_its->its_base + GITS_TYPER); > hw_its->devid_bits =3D GITS_TYPER_DEVICE_ID_BITS(reg); > hw_its->evid_bits =3D GITS_TYPER_EVENT_ID_BITS(reg); > @@ -1189,7 +1197,7 @@ static void gicv3_its_acpi_init(void) > =20 > #endif > =20 > -int gicv3_its_init(void) > +int __init gicv3_its_init(unsigned int host_lpi_bits) > { > struct host_its *hw_its; > int ret; > @@ -1201,13 +1209,27 @@ int gicv3_its_init(void) > =20 > list_for_each_entry(hw_its, &host_its_list, entry) > { > - ret =3D gicv3_its_init_single_its(hw_its); > + ret =3D gicv3_its_prepare_single_its(hw_its); > if ( ret ) > return ret; > } > =20 > gicv3_its_validate_quirks(); > =20 > + if ( list_empty(&host_its_list) ) > + return 0; What is the purpose of this check here? I'd expect to see it before the first list_for_each_entry() loop. > + > + ret =3D gicv3_lpi_init_host_lpis(host_lpi_bits); > + if ( ret ) > + return ret; > + > + list_for_each_entry(hw_its, &host_its_list, entry) > + { > + ret =3D gicv3_its_init_single_its(hw_its); > + if ( ret ) > + return ret; > + } > + > return 0; > } [...] --=20 WBR, Volodymyr=