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Berrange" Subject: Re: what is qemu_system_guest_panicked() for? In-Reply-To: References: <877bmz54i1.fsf@suse.de> Date: Mon, 13 Jul 2026 13:11:00 -0300 Message-ID: <8733xm6faj.fsf@suse.de> MIME-Version: 1.0 Content-Type: text/plain X-Spamd-Result: default: False [-3.30 / 50.00]; BAYES_HAM(-3.00)[99.99%]; SUBJECT_ENDS_QUESTION(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; FREEMAIL_ENVRCPT(0.00)[gmail.com]; RCVD_TLS_ALL(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; MISSING_XM_UA(0.00)[]; RCPT_COUNT_SEVEN(0.00)[11]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; TO_DN_ALL(0.00)[]; FROM_HAS_DN(0.00)[]; FREEMAIL_CC(0.00)[nongnu.org,redhat.com,microsoft.com,unpredictable.fr,gmail.com,linux.ibm.com]; MIME_TRACE(0.00)[0:+]; FROM_EQ_ENVFROM(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.de:email,suse.de:mid] Received-SPF: pass client-ip=195.135.223.131; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Peter Maydell writes: > On Mon, 13 Jul 2026 at 15:49, Fabiano Rosas wrote: >> >> Peter Maydell writes: >> > - ppc TCG, in powerpc_checkstop(), for a machine check exception I think >> >> 1) The Checkstop state is the state the (modern) architecture prescribes >> the machine transitions to when: a) machine check happens but machine >> check exceptions are disabled or b) hard-to-recover storage errors. On >> older user manuals I also see occurrences of checkstop when (a) above >> happens and a "debug bit" is also set. >> >> 603 UM: >> "[cpu] must terminate operation by internally gating off all clocks, and >> release all outputs to the high impedance state" >> >> 750cx UM: >> "When a processor is in checkstop state, instruction processing is >> suspended and generally cannot resume without the processor being >> reset." > > Thanks. So since this is in TCG, is this for the case "we emulated > the CPU ending up in a checkstop situation", rather than "the real > host hardware is broken" ? Can the guest deliberately provoke real > hardware into this state, or is it only something you can get into > when the h/w is broken ? > The former, checkstop emulation. The guest cannot cause real hardware to be in this state, this is the cosmic rays kind of problem.