From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3195D2C3276 for ; Wed, 17 Dec 2025 20:41:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766004092; cv=none; b=jtx7KKBZwUbbAGg3EnybyYOqmDebKRGedwS08wuUosgt2dfI2/y/OFMTxbMCitxMvGBtaHKuRz4R+tZUsmGy04xyFmAFnnaphvyDb6fdWCk4JftdUg4ebf9h3HEqNrofSUxMw/+aP3Dx09UEGQqrKPN0XUlnzCdwEP3QubN+snQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766004092; c=relaxed/simple; bh=gcN1TT6aF/L7+qSeaLMa/O7LiAP0XGyItQVCjdHMSKM=; h=From:To:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=eF/geUEdu79i1gAIW/5Wdm61TnNHX1zwsWV048poNAtD9B0tTt4WRFnXDqp6uqoKsQccBA/fgyad7y/pT9ysLKWD9c5UjYMccYBpajtnnSgDLWKNMv/GA3UfnwMSXHTx8RSVCPxz9IeY1LRMci/F5kPfmhPMwkM5obrCPR6cvXk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=PdKFnGbD; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=QsMBXxVU; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="PdKFnGbD"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="QsMBXxVU" From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1766004089; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=z79YFfbHi7X2HE5gzczHsc33jEvsoLS48XOk/su+1a0=; b=PdKFnGbDQeLAhYl2z5IM7kGUP9hebQ/vyhVt/igR2Aai4JJL6C0ISGFduoN4DfmCVZns88 V5yzlPPfEAovRk2a3rBYEHpcpbQF7CVqVKetL/TTXwTm9GLu0LyRVbuODO6R7eoJN42zvj GKJLo0sTIxHnHCzjUBmBsTuHxnNH+NrlKV+CLq5CtNMNXXJL8g9lQthuuIR67v8W7kEEsp JNI8J+Z4hYXpQ/CnkZcLcaCL6ihP6/TvpFevdflsnh9GCjt/0ZTXLsXSD03SevaSCUjMcg W8oyF+ZJ3Wqo+9gMWBtxEKM9Re4q0t4oo5KQUFshllB7RFzyduvN0VDUrx4kxA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1766004089; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=z79YFfbHi7X2HE5gzczHsc33jEvsoLS48XOk/su+1a0=; b=QsMBXxVUAV8W0xMOFiNlRd0MQdZbQ2q7N9W3VlkTnH8pP/3o1nscFszBiAd/Bh8QwpOl58 XCfRsg8R5Cw2OECw== To: Chao Xie , linux-kernel@vger.kernel.org Subject: Re: [irq-msi] questions about irq msi_desc usage In-Reply-To: References: Date: Wed, 17 Dec 2025 21:41:27 +0100 Message-ID: <873458deo8.ffs@tglx> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Wed, Dec 17 2025 at 09:58, Chao Xie wrote: > 1. To define my own private data structure, should I follow the PCI MSI > approach and add a structure like struct my_private_intr_desc to > the union? No. > I think I can make use of data.docckie.ptr to point to my private data > structure, but I do not find any example in kernel, and not sure whether > It is right or not. Yes it is the right thing to do if you really need private data for your driver. You did not explain what this data is used for and why it needs to be accessible through msi_desc, so I can't tell. > 2. If I use data.dcookie.ptr to point to my private data structure, > should this association be initialized in msi_domain_ops.set_desc()? prepare_desc() is probably the right place especially if you need access to the domain itself. > 3. The Type 1 interrupt of this bus is similar to MSI. Why are hardware people insisting on repeating the same mistakes over and over? > In this case, when allocating msi_desc, should I follow the PCI MSI > model where one msi_desc represents multiple interrupts > (i.e.,set msi_desc.nvec_used = n)? That's the only way you can guarantee consecutive Linux interrupt numbers for the block you allocate. > If this is the correct approach, > is itfeasible to add a judgment similar to PCI MSI in > msi_domain_get_virq() as follows: > if (dev_is_pci(dev) && domid == MSI_DEFAULT_DOMAIN) > devmsi = to_pci_dev(dev)->msi_enabled; > +++ if (dev_is_my_private(dev) && domid == MSI_DEFAULT_DOMAIN) > +++ devmsi = to_my_private_entity(dev)->is_type1; No. This wants to be generalized. Thanks, tglx