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[91.219.240.2]) by smtp.gmail.com with ESMTPSA id a18-20020a7bc1d2000000b003942a244ee2sm2731791wmj.39.2022.05.12.07.05.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 07:05:22 -0700 (PDT) From: Vitaly Kuznetsov To: Paolo Bonzini , qemu-devel@nongnu.org Subject: Re: [PATCH] vmxcap: add tertiary execution controls In-Reply-To: <20220511165244.336750-1-pbonzini@redhat.com> References: <20220511165244.336750-1-pbonzini@redhat.com> Date: Thu, 12 May 2022 16:05:21 +0200 Message-ID: <8735heyhge.fsf@redhat.com> MIME-Version: 1.0 Content-Type: text/plain Received-SPF: pass client-ip=170.10.129.124; envelope-from=vkuznets@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Paolo Bonzini writes: > Signed-off-by: Paolo Bonzini > --- > scripts/kvm/vmxcap | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/scripts/kvm/vmxcap b/scripts/kvm/vmxcap > index f140040104..ce27f5e635 100755 > --- a/scripts/kvm/vmxcap > +++ b/scripts/kvm/vmxcap > @@ -23,6 +23,7 @@ MSR_IA32_VMX_TRUE_PROCBASED_CTLS = 0x48E > MSR_IA32_VMX_TRUE_EXIT_CTLS = 0x48F > MSR_IA32_VMX_TRUE_ENTRY_CTLS = 0x490 > MSR_IA32_VMX_VMFUNC = 0x491 > +MSR_IA32_VMX_PROCBASED_CTLS3 = 0x492 > > class msr(object): > def __init__(self): > @@ -71,6 +72,13 @@ class Control(object): > s = 'yes' > print(' %-40s %s' % (self.bits[bit], s)) > > +# All 64 bits in the tertiary controls MSR are allowed-1 > +class Allowed1Control(Control): > + def read2(self, nr): > + m = msr() > + val = m.read(nr, 0) > + return (0, val) > + > class Misc(object): > def __init__(self, name, bits, msr): > self.name = name > @@ -135,6 +143,7 @@ controls = [ > 12: 'RDTSC exiting', > 15: 'CR3-load exiting', > 16: 'CR3-store exiting', > + 17: 'Activate tertiary controls', > 19: 'CR8-load exiting', > 20: 'CR8-store exiting', > 21: 'Use TPR shadow', > @@ -186,6 +195,14 @@ controls = [ > cap_msr = MSR_IA32_VMX_PROCBASED_CTLS2, > ), > > + Allowed1Control( > + name = 'tertiary processor-based controls', > + bits = { > + 4: 'Enable IPI virtualization' > + }, > + cap_msr = MSR_IA32_VMX_PROCBASED_CTLS3, > + ), > + > Control( > name = 'VM-Exit controls', > bits = { Not sure which particular CPUs are going to implement this (whould be nice to add this info to the blurb) but this matches Intel doc (https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html) and "IPI virtualization support for VM" series for KVM, so Reviewed-by: Vitaly Kuznetsov -- Vitaly