From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id l15sm2786391wmh.6.2022.01.18.09.31.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jan 2022 09:31:27 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id C6C0A1FFB7; Tue, 18 Jan 2022 17:31:26 +0000 (GMT) References: <20220111171048.3545974-1-peter.maydell@linaro.org> <20220111171048.3545974-12-peter.maydell@linaro.org> User-agent: mu4e 1.7.5; emacs 28.0.91 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Shashi Mallela Subject: Re: [PATCH v2 11/13] hw/intc/arm_gicv3_its: Factor out "find address of table entry" code Date: Tue, 18 Jan 2022 17:31:20 +0000 In-reply-to: <20220111171048.3545974-12-peter.maydell@linaro.org> Message-ID: <8735ll9ci9.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-TUID: WKmfeTDNtI/P Peter Maydell writes: > The ITS has several tables which all share a similar format, > described by the TableDesc struct: the guest may configure them > to be a single-level table or a two-level table. Currently we > open-code the process of finding the table entry in all the > functions which read or write the device table or the collection > table. Factor out the "get the address of the table entry" > logic into a new function, so that the code which needs to > read or write a table entry only needs to call table_entry_addr() > and then perform a suitable load or store to that address. > > Note that the error handling is slightly complicated because > we want to handle two cases differently: > * failure to read the L1 table entry should end up causing > a command stall, like other kinds of DMA error > * an L1 table entry that says there is no L2 table for this > index (ie whose valid bit is 0) must result in us treating > the table entry as not-valid on read, and discarding > writes (this is mandated by the spec) > > Signed-off-by: Peter Maydell > Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E83F9C433EF for ; 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Tue, 18 Jan 2022 09:31:28 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id l15sm2786391wmh.6.2022.01.18.09.31.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jan 2022 09:31:27 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id C6C0A1FFB7; Tue, 18 Jan 2022 17:31:26 +0000 (GMT) References: <20220111171048.3545974-1-peter.maydell@linaro.org> <20220111171048.3545974-12-peter.maydell@linaro.org> User-agent: mu4e 1.7.5; emacs 28.0.91 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Peter Maydell Subject: Re: [PATCH v2 11/13] hw/intc/arm_gicv3_its: Factor out "find address of table entry" code Date: Tue, 18 Jan 2022 17:31:20 +0000 In-reply-to: <20220111171048.3545974-12-peter.maydell@linaro.org> Message-ID: <8735ll9ci9.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32c (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shashi Mallela , qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Peter Maydell writes: > The ITS has several tables which all share a similar format, > described by the TableDesc struct: the guest may configure them > to be a single-level table or a two-level table. Currently we > open-code the process of finding the table entry in all the > functions which read or write the device table or the collection > table. Factor out the "get the address of the table entry" > logic into a new function, so that the code which needs to > read or write a table entry only needs to call table_entry_addr() > and then perform a suitable load or store to that address. > > Note that the error handling is slightly complicated because > we want to handle two cases differently: > * failure to read the L1 table entry should end up causing > a command stall, like other kinds of DMA error > * an L1 table entry that says there is no L2 table for this > index (ie whose valid bit is 0) must result in us treating > the table entry as not-valid on read, and discarding > writes (this is mandated by the spec) > > Signed-off-by: Peter Maydell > Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e