From mboxrd@z Thu Jan 1 00:00:00 1970 From: jani.nikula@intel.com (Jani Nikula) Date: Wed, 24 Jan 2018 13:53:48 +0200 Subject: REGRESSION in c5552fde102f ("nvme: Enable autonomous power state transitions") In-Reply-To: <87shaveb5b.fsf@intel.com> References: <87shaveb5b.fsf@intel.com> Message-ID: <87372vealv.fsf@intel.com> [Fixed Ville's address, sorry for the extra noise.] On Wed, 24 Jan 2018, Jani Nikula wrote: > Hi Andy, all - > > So this is an odd one. > > I'm getting display FIFO underruns in a very specific setting: Laptop > display switched off, and an external display connected. Other > combinations work fine. > > I've bisected this to c5552fde102f ("nvme: Enable autonomous power state > transitions"), and, being baffled by the result, carefully checked > this. There are no problems when running c5552fde102f^, with > nvme_core.default_ps_max_latency_us=0, or after 'echo 0 > > pm_qos_latency_tolerance_us'. With the last one, restoring the original > value of 100000 brings the underruns back. > > I have no idea what the root cause mechanism here is, but the bisect is > correct. Perhaps something to do with timing. I'd be happy to provide > further details. > > I see that you have quirked one Samsung device. Incidentally, this > Lenovo Yoga 910 (Kabylake, SunrisePoint LP PCH) also has a Samsung NVMe > device, just a different one. Details below. I don't know what the > failure mode in the quirked one is, so I don't know if this could be the > same issue. > > BR, > Jani. > > > $ lspci -vvnn -s 02:00.0 > 02:00.0 Non-Volatile memory controller [0108]: Samsung Electronics Co Ltd Device [144d:a804] (prog-if 02 [NVM Express]) > Subsystem: Samsung Electronics Co Ltd Device [144d:a801] > Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- Latency: 0, Cache Line Size: 64 bytes > Interrupt: pin A routed to IRQ 16 > NUMA node: 0 > Region 0: Memory at a1200000 (64-bit, non-prefetchable) [size=16K] > Capabilities: [40] Power Management version 3 > Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) > Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [50] MSI: Enable- Count=1/32 Maskable- 64bit+ > Address: 0000000000000000 Data: 0000 > Capabilities: [70] Express (v2) Endpoint, MSI 00 > DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited > ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 25.000W > DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ > RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset- > MaxPayload 256 bytes, MaxReadReq 512 bytes > DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- > LnkCap: Port #0, Speed 8GT/s, Width x4, ASPM L1, Exit Latency L0s unlimited, L1 <64us > ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ > LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+ > ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt- > LnkSta: Speed 8GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- > DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR+, OBFF Not Supported > DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled > LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis- > Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- > Compliance De-emphasis: -6dB > LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+, EqualizationPhase1+ > EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest- > Capabilities: [b0] MSI-X: Enable+ Count=33 Masked- > Vector table: BAR=0 offset=00003000 > PBA: BAR=0 offset=00002000 > Capabilities: [100 v2] Advanced Error Reporting > UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- > UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- > UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- > CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- > CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ > AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- > Capabilities: [148 v1] Device Serial Number 00-00-00-00-00-00-00-00 > Capabilities: [158 v1] Power Budgeting > Capabilities: [168 v1] #19 > Capabilities: [188 v1] Latency Tolerance Reporting > Max snoop latency: 3145728ns > Max no snoop latency: 3145728ns > Capabilities: [190 v1] L1 PM Substates > L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ > PortCommonModeRestoreTime=10us PortTPowerOnTime=10us > L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ > T_CommonMode=0us LTR1.2_Threshold=163840ns > L1SubCtl2: T_PwrOn=44us > Kernel driver in use: nvme > Kernel modules: nvme -- Jani Nikula, Intel Open Source Technology Center From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: REGRESSION in c5552fde102f ("nvme: Enable autonomous power state transitions") Date: Wed, 24 Jan 2018 13:53:48 +0200 Message-ID: <87372vealv.fsf@intel.com> References: <87shaveb5b.fsf@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 297C06E5C0 for ; Wed, 24 Jan 2018 11:48:38 +0000 (UTC) In-Reply-To: <87shaveb5b.fsf@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Andy Lutomirski , Keith Busch , Jens Axboe , Christoph Hellwig , Sagi Grimberg , linux-nvme@lists.infradead.org Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org CltGaXhlZCBWaWxsZSdzIGFkZHJlc3MsIHNvcnJ5IGZvciB0aGUgZXh0cmEgbm9pc2UuXQoKT24g V2VkLCAyNCBKYW4gMjAxOCwgSmFuaSBOaWt1bGEgPGphbmkubmlrdWxhQGludGVsLmNvbT4gd3Jv dGU6Cj4gSGkgQW5keSwgYWxsIC0KPgo+IFNvIHRoaXMgaXMgYW4gb2RkIG9uZS4KPgo+IEknbSBn ZXR0aW5nIGRpc3BsYXkgRklGTyB1bmRlcnJ1bnMgaW4gYSB2ZXJ5IHNwZWNpZmljIHNldHRpbmc6 IExhcHRvcAo+IGRpc3BsYXkgc3dpdGNoZWQgb2ZmLCBhbmQgYW4gZXh0ZXJuYWwgZGlzcGxheSBj b25uZWN0ZWQuIE90aGVyCj4gY29tYmluYXRpb25zIHdvcmsgZmluZS4KPgo+IEkndmUgYmlzZWN0 ZWQgdGhpcyB0byBjNTU1MmZkZTEwMmYgKCJudm1lOiBFbmFibGUgYXV0b25vbW91cyBwb3dlciBz dGF0ZQo+IHRyYW5zaXRpb25zIiksIGFuZCwgYmVpbmcgYmFmZmxlZCBieSB0aGUgcmVzdWx0LCBj YXJlZnVsbHkgY2hlY2tlZAo+IHRoaXMuIFRoZXJlIGFyZSBubyBwcm9ibGVtcyB3aGVuIHJ1bm5p bmcgYzU1NTJmZGUxMDJmXiwgd2l0aAo+IG52bWVfY29yZS5kZWZhdWx0X3BzX21heF9sYXRlbmN5 X3VzPTAsIG9yIGFmdGVyICdlY2hvIDAgPgo+IHBtX3Fvc19sYXRlbmN5X3RvbGVyYW5jZV91cycu IFdpdGggdGhlIGxhc3Qgb25lLCByZXN0b3JpbmcgdGhlIG9yaWdpbmFsCj4gdmFsdWUgb2YgMTAw MDAwIGJyaW5ncyB0aGUgdW5kZXJydW5zIGJhY2suCj4KPiBJIGhhdmUgbm8gaWRlYSB3aGF0IHRo ZSByb290IGNhdXNlIG1lY2hhbmlzbSBoZXJlIGlzLCBidXQgdGhlIGJpc2VjdCBpcwo+IGNvcnJl Y3QuIFBlcmhhcHMgc29tZXRoaW5nIHRvIGRvIHdpdGggdGltaW5nLiBJJ2QgYmUgaGFwcHkgdG8g cHJvdmlkZQo+IGZ1cnRoZXIgZGV0YWlscy4KPgo+IEkgc2VlIHRoYXQgeW91IGhhdmUgcXVpcmtl ZCBvbmUgU2Ftc3VuZyBkZXZpY2UuIEluY2lkZW50YWxseSwgdGhpcwo+IExlbm92byBZb2dhIDkx MCAoS2FieWxha2UsIFN1bnJpc2VQb2ludCBMUCBQQ0gpIGFsc28gaGFzIGEgU2Ftc3VuZyBOVk1l Cj4gZGV2aWNlLCBqdXN0IGEgZGlmZmVyZW50IG9uZS4gRGV0YWlscyBiZWxvdy4gSSBkb24ndCBr bm93IHdoYXQgdGhlCj4gZmFpbHVyZSBtb2RlIGluIHRoZSBxdWlya2VkIG9uZSBpcywgc28gSSBk b24ndCBrbm93IGlmIHRoaXMgY291bGQgYmUgdGhlCj4gc2FtZSBpc3N1ZS4KPgo+IEJSLAo+IEph bmkuCj4KPgo+ICQgbHNwY2kgLXZ2bm4gLXMgMDI6MDAuMAo+IDAyOjAwLjAgTm9uLVZvbGF0aWxl IG1lbW9yeSBjb250cm9sbGVyIFswMTA4XTogU2Ftc3VuZyBFbGVjdHJvbmljcyBDbyBMdGQgRGV2 aWNlIFsxNDRkOmE4MDRdIChwcm9nLWlmIDAyIFtOVk0gRXhwcmVzc10pCj4gCVN1YnN5c3RlbTog U2Ftc3VuZyBFbGVjdHJvbmljcyBDbyBMdGQgRGV2aWNlIFsxNDRkOmE4MDFdCj4gCUNvbnRyb2w6 IEkvTy0gTWVtKyBCdXNNYXN0ZXIrIFNwZWNDeWNsZS0gTWVtV0lOVi0gVkdBU25vb3AtIFBhckVy ci0gU3RlcHBpbmctIFNFUlItIEZhc3RCMkItIERpc0lOVHgrCj4gCVN0YXR1czogQ2FwKyA2Nk1I ei0gVURGLSBGYXN0QjJCLSBQYXJFcnItIERFVlNFTD1mYXN0ID5UQWJvcnQtIDxUQWJvcnQtIDxN QWJvcnQtID5TRVJSLSA8UEVSUi0gSU5UeC0KPiAJTGF0ZW5jeTogMCwgQ2FjaGUgTGluZSBTaXpl OiA2NCBieXRlcwo+IAlJbnRlcnJ1cHQ6IHBpbiBBIHJvdXRlZCB0byBJUlEgMTYKPiAJTlVNQSBu b2RlOiAwCj4gCVJlZ2lvbiAwOiBNZW1vcnkgYXQgYTEyMDAwMDAgKDY0LWJpdCwgbm9uLXByZWZl dGNoYWJsZSkgW3NpemU9MTZLXQo+IAlDYXBhYmlsaXRpZXM6IFs0MF0gUG93ZXIgTWFuYWdlbWVu dCB2ZXJzaW9uIDMKPiAJCUZsYWdzOiBQTUVDbGstIERTSS0gRDEtIEQyLSBBdXhDdXJyZW50PTBt QSBQTUUoRDAtLEQxLSxEMi0sRDNob3QtLEQzY29sZC0pCj4gCQlTdGF0dXM6IEQwIE5vU29mdFJz dCsgUE1FLUVuYWJsZS0gRFNlbD0wIERTY2FsZT0wIFBNRS0KPiAJQ2FwYWJpbGl0aWVzOiBbNTBd IE1TSTogRW5hYmxlLSBDb3VudD0xLzMyIE1hc2thYmxlLSA2NGJpdCsKPiAJCUFkZHJlc3M6IDAw MDAwMDAwMDAwMDAwMDAgIERhdGE6IDAwMDAKPiAJQ2FwYWJpbGl0aWVzOiBbNzBdIEV4cHJlc3Mg KHYyKSBFbmRwb2ludCwgTVNJIDAwCj4gCQlEZXZDYXA6CU1heFBheWxvYWQgMjU2IGJ5dGVzLCBQ aGFudEZ1bmMgMCwgTGF0ZW5jeSBMMHMgdW5saW1pdGVkLCBMMSB1bmxpbWl0ZWQKPiAJCQlFeHRU YWctIEF0dG5CdG4tIEF0dG5JbmQtIFB3ckluZC0gUkJFKyBGTFJlc2V0KyBTbG90UG93ZXJMaW1p dCAyNS4wMDBXCj4gCQlEZXZDdGw6CVJlcG9ydCBlcnJvcnM6IENvcnJlY3RhYmxlKyBOb24tRmF0 YWwrIEZhdGFsKyBVbnN1cHBvcnRlZCsKPiAJCQlSbHhkT3JkKyBFeHRUYWctIFBoYW50RnVuYy0g QXV4UHdyLSBOb1Nub29wKyBGTFJlc2V0LQo+IAkJCU1heFBheWxvYWQgMjU2IGJ5dGVzLCBNYXhS ZWFkUmVxIDUxMiBieXRlcwo+IAkJRGV2U3RhOglDb3JyRXJyLSBVbmNvcnJFcnItIEZhdGFsRXJy LSBVbnN1cHBSZXEtIEF1eFB3cisgVHJhbnNQZW5kLQo+IAkJTG5rQ2FwOglQb3J0ICMwLCBTcGVl ZCA4R1QvcywgV2lkdGggeDQsIEFTUE0gTDEsIEV4aXQgTGF0ZW5jeSBMMHMgdW5saW1pdGVkLCBM MSA8NjR1cwo+IAkJCUNsb2NrUE0rIFN1cnByaXNlLSBMTEFjdFJlcC0gQndOb3QtIEFTUE1PcHRD b21wKwo+IAkJTG5rQ3RsOglBU1BNIEwxIEVuYWJsZWQ7IFJDQiA2NCBieXRlcyBEaXNhYmxlZC0g Q29tbUNsaysKPiAJCQlFeHRTeW5jaC0gQ2xvY2tQTSsgQXV0V2lkRGlzLSBCV0ludC0gQXV0QldJ bnQtCj4gCQlMbmtTdGE6CVNwZWVkIDhHVC9zLCBXaWR0aCB4NCwgVHJFcnItIFRyYWluLSBTbG90 Q2xrKyBETEFjdGl2ZS0gQldNZ210LSBBQldNZ210LQo+IAkJRGV2Q2FwMjogQ29tcGxldGlvbiBU aW1lb3V0OiBSYW5nZSBBQkNELCBUaW1lb3V0RGlzKywgTFRSKywgT0JGRiBOb3QgU3VwcG9ydGVk Cj4gCQlEZXZDdGwyOiBDb21wbGV0aW9uIFRpbWVvdXQ6IDUwdXMgdG8gNTBtcywgVGltZW91dERp cy0sIExUUissIE9CRkYgRGlzYWJsZWQKPiAJCUxua0N0bDI6IFRhcmdldCBMaW5rIFNwZWVkOiA4 R1QvcywgRW50ZXJDb21wbGlhbmNlLSBTcGVlZERpcy0KPiAJCQkgVHJhbnNtaXQgTWFyZ2luOiBO b3JtYWwgT3BlcmF0aW5nIFJhbmdlLCBFbnRlck1vZGlmaWVkQ29tcGxpYW5jZS0gQ29tcGxpYW5j ZVNPUy0KPiAJCQkgQ29tcGxpYW5jZSBEZS1lbXBoYXNpczogLTZkQgo+IAkJTG5rU3RhMjogQ3Vy cmVudCBEZS1lbXBoYXNpcyBMZXZlbDogLTZkQiwgRXF1YWxpemF0aW9uQ29tcGxldGUrLCBFcXVh bGl6YXRpb25QaGFzZTErCj4gCQkJIEVxdWFsaXphdGlvblBoYXNlMissIEVxdWFsaXphdGlvblBo YXNlMyssIExpbmtFcXVhbGl6YXRpb25SZXF1ZXN0LQo+IAlDYXBhYmlsaXRpZXM6IFtiMF0gTVNJ LVg6IEVuYWJsZSsgQ291bnQ9MzMgTWFza2VkLQo+IAkJVmVjdG9yIHRhYmxlOiBCQVI9MCBvZmZz ZXQ9MDAwMDMwMDAKPiAJCVBCQTogQkFSPTAgb2Zmc2V0PTAwMDAyMDAwCj4gCUNhcGFiaWxpdGll czogWzEwMCB2Ml0gQWR2YW5jZWQgRXJyb3IgUmVwb3J0aW5nCj4gCQlVRVN0YToJRExQLSBTREVT LSBUTFAtIEZDUC0gQ21wbHRUTy0gQ21wbHRBYnJ0LSBVbnhDbXBsdC0gUnhPRi0gTWFsZlRMUC0g RUNSQy0gVW5zdXBSZXEtIEFDU1Zpb2wtCj4gCQlVRU1zazoJRExQLSBTREVTLSBUTFAtIEZDUC0g Q21wbHRUTy0gQ21wbHRBYnJ0LSBVbnhDbXBsdC0gUnhPRi0gTWFsZlRMUC0gRUNSQy0gVW5zdXBS ZXEtIEFDU1Zpb2wtCj4gCQlVRVN2cnQ6CURMUCsgU0RFUysgVExQLSBGQ1ArIENtcGx0VE8tIENt cGx0QWJydC0gVW54Q21wbHQtIFJ4T0YrIE1hbGZUTFArIEVDUkMtIFVuc3VwUmVxLSBBQ1NWaW9s LQo+IAkJQ0VTdGE6CVJ4RXJyLSBCYWRUTFAtIEJhZERMTFAtIFJvbGxvdmVyLSBUaW1lb3V0LSBO b25GYXRhbEVyci0KPiAJCUNFTXNrOglSeEVyci0gQmFkVExQLSBCYWRETExQLSBSb2xsb3Zlci0g VGltZW91dC0gTm9uRmF0YWxFcnIrCj4gCQlBRVJDYXA6CUZpcnN0IEVycm9yIFBvaW50ZXI6IDAw LCBHZW5DYXArIENHZW5Fbi0gQ2hrQ2FwKyBDaGtFbi0KPiAJQ2FwYWJpbGl0aWVzOiBbMTQ4IHYx XSBEZXZpY2UgU2VyaWFsIE51bWJlciAwMC0wMC0wMC0wMC0wMC0wMC0wMC0wMAo+IAlDYXBhYmls aXRpZXM6IFsxNTggdjFdIFBvd2VyIEJ1ZGdldGluZyA8Pz4KPiAJQ2FwYWJpbGl0aWVzOiBbMTY4 IHYxXSAjMTkKPiAJQ2FwYWJpbGl0aWVzOiBbMTg4IHYxXSBMYXRlbmN5IFRvbGVyYW5jZSBSZXBv cnRpbmcKPiAJCU1heCBzbm9vcCBsYXRlbmN5OiAzMTQ1NzI4bnMKPiAJCU1heCBubyBzbm9vcCBs YXRlbmN5OiAzMTQ1NzI4bnMKPiAJQ2FwYWJpbGl0aWVzOiBbMTkwIHYxXSBMMSBQTSBTdWJzdGF0 ZXMKPiAJCUwxU3ViQ2FwOiBQQ0ktUE1fTDEuMisgUENJLVBNX0wxLjErIEFTUE1fTDEuMisgQVNQ TV9MMS4xKyBMMV9QTV9TdWJzdGF0ZXMrCj4gCQkJICBQb3J0Q29tbW9uTW9kZVJlc3RvcmVUaW1l PTEwdXMgUG9ydFRQb3dlck9uVGltZT0xMHVzCj4gCQlMMVN1YkN0bDE6IFBDSS1QTV9MMS4yKyBQ Q0ktUE1fTDEuMSsgQVNQTV9MMS4yKyBBU1BNX0wxLjErCj4gCQkJICAgVF9Db21tb25Nb2RlPTB1 cyBMVFIxLjJfVGhyZXNob2xkPTE2Mzg0MG5zCj4gCQlMMVN1YkN0bDI6IFRfUHdyT249NDR1cwo+ IAlLZXJuZWwgZHJpdmVyIGluIHVzZTogbnZtZQo+IAlLZXJuZWwgbW9kdWxlczogbnZtZQoKLS0g CkphbmkgTmlrdWxhLCBJbnRlbCBPcGVuIFNvdXJjZSBUZWNobm9sb2d5IENlbnRlcgpfX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpJbnRlbC1nZnggbWFpbGlu ZyBsaXN0CkludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVl ZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK