From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mika Kuoppala Subject: Re: [PATCH v2 1/3] drm/i915/execlists: Wrap tail pointer after reset tweaking Date: Mon, 27 Mar 2017 16:05:04 +0300 Message-ID: <8737dyyinz.fsf@gaia.fi.intel.com> References: <20170327130009.4678-1-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 406CE6E1E3 for ; Mon, 27 Mar 2017 13:05:29 +0000 (UTC) In-Reply-To: <20170327130009.4678-1-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson , intel-gfx@lists.freedesktop.org Cc: "# v4 . 10+" List-Id: intel-gfx@lists.freedesktop.org Q2hyaXMgV2lsc29uIDxjaHJpc0BjaHJpcy13aWxzb24uY28udWs+IHdyaXRlczoKCj4gSWYgdGhl IHJlcXVlc3QtPndhX3RhaWwgaXMgMCAoYmVjYXVzZSBpdCBsYW5kZWQgZXhhY3RseSBvbiB0aGUg ZW5kIG9mCj4gdGhlIHJpbmdidWZmZXIpLCB3aGVuIHdlIHJlY29uc3RydWN0IHJlcXVlc3QtPnRh aWwgZm9sbG93aW5nIGEgcmVzZXQgd2UKPiBmaWxsIGluIGFuIGlsbGVnYWwgdmFsdWUgKC04IG9y IDB4MDAxZmZmZjgpLiBBcyBhIHJlc3VsdCwgUklOR19IRUFEIGlzCj4gbmV2ZXIgYWJsZSB0byBj YXRjaCB1cCB3aXRoIFJJTkdfVEFJTCBhbmQgdGhlIEdQVSBzcGlucyBlbmRsZXNzbHkuIElmCj4g dGhlIHJpbmcgY29udGFpbnMgYSBjb3VwbGUgb2YgYnJlYWRjcnVtYnMsIGV2ZW4gb3VyIGhhbmdj aGVjayBpcyB1bmFibGUKPiB0byBjYXRjaCB0aGUgYnVzeS1sb29waW5nIGFzIHRoZSBBQ1RIRCBh bmQgc2Vxbm8gY29udGludWFsbHkgYWR2YW5jZS4KPgo+IHYyOiBNb3ZlIHRoZSB3cmFwIGludG8g YSBjb21tb24gaW50ZWxfcmluZ193cmFwKCkuCj4KPiBGaXhlczogYTNhYWJlODZhMzQwICgiZHJt L2k5MTUvZXhlY2xpc3RzOiBSZWluaXRpYWxpc2UgY29udGV4dCBpbWFnZSBhZnRlciBHUFUgaGFu ZyIpCj4gU2lnbmVkLW9mZi1ieTogQ2hyaXMgV2lsc29uIDxjaHJpc0BjaHJpcy13aWxzb24uY28u dWs+Cj4gQ2M6IE1pa2EgS3VvcHBhbGEgPG1pa2Eua3VvcHBhbGFAaW50ZWwuY29tPgo+IENjOiA8 c3RhYmxlQHZnZXIua2VybmVsLm9yZz4gIyB2NC4xMCsKClJldmlld2VkLWJ5OiBNaWthIEt1b3Bw YWxhIDxtaWthLmt1b3BwYWxhQGludGVsLmNvbT4KCj4gLS0tCj4gIGRyaXZlcnMvZ3B1L2RybS9p OTE1L2ludGVsX2xyYy5jICAgICAgICB8ICA0ICsrKy0KPiAgZHJpdmVycy9ncHUvZHJtL2k5MTUv aW50ZWxfcmluZ2J1ZmZlci5oIHwgMTAgKysrKysrKystLQo+ICAyIGZpbGVzIGNoYW5nZWQsIDEx IGluc2VydGlvbnMoKyksIDMgZGVsZXRpb25zKC0pCj4KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9n cHUvZHJtL2k5MTUvaW50ZWxfbHJjLmMgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9scmMu Ywo+IGluZGV4IGI3NWRmNzBlOGUwZS4uMzJmYjhhZDNmZDM2IDEwMDY0NAo+IC0tLSBhL2RyaXZl cnMvZ3B1L2RybS9pOTE1L2ludGVsX2xyYy5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUv aW50ZWxfbHJjLmMKPiBAQCAtMTI3OCw3ICsxMjc4LDkgQEAgc3RhdGljIHZvaWQgcmVzZXRfY29t bW9uX3Jpbmcoc3RydWN0IGludGVsX2VuZ2luZV9jcyAqZW5naW5lLAo+ICAJR0VNX0JVR19PTihy ZXF1ZXN0LT5jdHggIT0gcG9ydFswXS5yZXF1ZXN0LT5jdHgpOwo+ICAKPiAgCS8qIFJlc2V0IFdh SWRsZUxpdGVSZXN0b3JlOmJkdyxza2wgYXMgd2VsbCAqLwo+IC0JcmVxdWVzdC0+dGFpbCA9IHJl cXVlc3QtPndhX3RhaWwgLSBXQV9UQUlMX0RXT1JEUyAqIHNpemVvZih1MzIpOwo+ICsJcmVxdWVz dC0+dGFpbCA9Cj4gKwkJaW50ZWxfcmluZ193cmFwKHJlcXVlc3QtPnJpbmcsCj4gKwkJCQlyZXF1 ZXN0LT53YV90YWlsIC0gV0FfVEFJTF9EV09SRFMqc2l6ZW9mKHUzMikpOwo+ICAJR0VNX0JVR19P TighSVNfQUxJR05FRChyZXF1ZXN0LT50YWlsLCA4KSk7Cj4gIH0KPiAgCj4gZGlmZiAtLWdpdCBh L2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX3JpbmdidWZmZXIuaCBiL2RyaXZlcnMvZ3B1L2Ry bS9pOTE1L2ludGVsX3JpbmdidWZmZXIuaAo+IGluZGV4IDE2NmFhMWFlNjVjZi4uMTdhYzQ0OTgw ZDg0IDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX3JpbmdidWZmZXIu aAo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX3JpbmdidWZmZXIuaAo+IEBAIC01 MTUsMTIgKzUxNSwxOCBAQCBpbnRlbF9yaW5nX2FkdmFuY2Uoc3RydWN0IGRybV9pOTE1X2dlbV9y ZXF1ZXN0ICpyZXEsIHUzMiAqY3MpCj4gIH0KPiAgCj4gIHN0YXRpYyBpbmxpbmUgdTMyCj4gLWlu dGVsX3Jpbmdfb2Zmc2V0KHN0cnVjdCBkcm1faTkxNV9nZW1fcmVxdWVzdCAqcmVxLCB2b2lkICph ZGRyKQo+ICtpbnRlbF9yaW5nX3dyYXAoY29uc3Qgc3RydWN0IGludGVsX3JpbmcgKnJpbmcsIHUz MiBwb3MpCj4gK3sKPiArCXJldHVybiBwb3MgJiAocmluZy0+c2l6ZSAtIDEpOwo+ICt9Cj4gKwo+ ICtzdGF0aWMgaW5saW5lIHUzMgo+ICtpbnRlbF9yaW5nX29mZnNldChjb25zdCBzdHJ1Y3QgZHJt X2k5MTVfZ2VtX3JlcXVlc3QgKnJlcSwgdm9pZCAqYWRkcikKPiAgewo+ICAJLyogRG9uJ3Qgd3Jp dGUgcmluZy0+c2l6ZSAoZXF1aXZhbGVudCB0byAwKSBhcyB0aGF0IGhhbmdzIHNvbWUgR1BVcy4g Ki8KPiAgCXUzMiBvZmZzZXQgPSBhZGRyIC0gcmVxLT5yaW5nLT52YWRkcjsKPiAgCUdFTV9CVUdf T04ob2Zmc2V0ID4gcmVxLT5yaW5nLT5zaXplKTsKPiAtCXJldHVybiBvZmZzZXQgJiAocmVxLT5y aW5nLT5zaXplIC0gMSk7Cj4gKwlyZXR1cm4gaW50ZWxfcmluZ193cmFwKHJlcS0+cmluZywgb2Zm c2V0KTsKPiAgfQo+ICAKPiAgdm9pZCBpbnRlbF9yaW5nX3VwZGF0ZV9zcGFjZShzdHJ1Y3QgaW50 ZWxfcmluZyAqcmluZyk7Cj4gLS0gCj4gMi4xMS4wCl9fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fCkludGVsLWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwtZ2Z4QGxp c3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFu L2xpc3RpbmZvL2ludGVsLWdmeAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com ([192.55.52.115]:47087 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752195AbdC0NGK (ORCPT ); Mon, 27 Mar 2017 09:06:10 -0400 From: Mika Kuoppala To: Chris Wilson , intel-gfx@lists.freedesktop.org Cc: tvrtko.ursulin@intel.com, Chris Wilson , "# v4 . 10+" Subject: Re: [PATCH v2 1/3] drm/i915/execlists: Wrap tail pointer after reset tweaking In-Reply-To: <20170327130009.4678-1-chris@chris-wilson.co.uk> References: <20170327130009.4678-1-chris@chris-wilson.co.uk> Date: Mon, 27 Mar 2017 16:05:04 +0300 Message-ID: <8737dyyinz.fsf@gaia.fi.intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: stable-owner@vger.kernel.org List-ID: Chris Wilson writes: > If the request->wa_tail is 0 (because it landed exactly on the end of > the ringbuffer), when we reconstruct request->tail following a reset we > fill in an illegal value (-8 or 0x001ffff8). As a result, RING_HEAD is > never able to catch up with RING_TAIL and the GPU spins endlessly. If > the ring contains a couple of breadcrumbs, even our hangcheck is unable > to catch the busy-looping as the ACTHD and seqno continually advance. > > v2: Move the wrap into a common intel_ring_wrap(). > > Fixes: a3aabe86a340 ("drm/i915/execlists: Reinitialise context image after GPU hang") > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala > Cc: # v4.10+ Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/intel_lrc.c | 4 +++- > drivers/gpu/drm/i915/intel_ringbuffer.h | 10 ++++++++-- > 2 files changed, 11 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index b75df70e8e0e..32fb8ad3fd36 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1278,7 +1278,9 @@ static void reset_common_ring(struct intel_engine_cs *engine, > GEM_BUG_ON(request->ctx != port[0].request->ctx); > > /* Reset WaIdleLiteRestore:bdw,skl as well */ > - request->tail = request->wa_tail - WA_TAIL_DWORDS * sizeof(u32); > + request->tail = > + intel_ring_wrap(request->ring, > + request->wa_tail - WA_TAIL_DWORDS*sizeof(u32)); > GEM_BUG_ON(!IS_ALIGNED(request->tail, 8)); > } > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h > index 166aa1ae65cf..17ac44980d84 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h > @@ -515,12 +515,18 @@ intel_ring_advance(struct drm_i915_gem_request *req, u32 *cs) > } > > static inline u32 > -intel_ring_offset(struct drm_i915_gem_request *req, void *addr) > +intel_ring_wrap(const struct intel_ring *ring, u32 pos) > +{ > + return pos & (ring->size - 1); > +} > + > +static inline u32 > +intel_ring_offset(const struct drm_i915_gem_request *req, void *addr) > { > /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */ > u32 offset = addr - req->ring->vaddr; > GEM_BUG_ON(offset > req->ring->size); > - return offset & (req->ring->size - 1); > + return intel_ring_wrap(req->ring, offset); > } > > void intel_ring_update_space(struct intel_ring *ring); > -- > 2.11.0