From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH 1/2] drm/i915/gen9: fix watermarks when using the pipe scaler Date: Mon, 10 Oct 2016 12:01:35 +0300 Message-ID: <8737k4tw5s.fsf@intel.com> References: <1475872138-16194-1-git-send-email-paulo.r.zanoni@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id CD2636E3D6 for ; Mon, 10 Oct 2016 09:01:37 +0000 (UTC) In-Reply-To: <1475872138-16194-1-git-send-email-paulo.r.zanoni@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org Cc: dhinakaran.pandiyan@intel.com, stable@vger.kernel.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org T24gRnJpLCAwNyBPY3QgMjAxNiwgUGF1bG8gWmFub25pIDxwYXVsby5yLnphbm9uaUBpbnRlbC5j b20+IHdyb3RlOgo+IEx1Y2tpbHksIHRoZSBuZWNlc3NhcnkgYWRqdXN0bWVudHMgZm9yIHdoZW4g d2UncmUgdXNpbmcgdGhlIHNjYWxlciBhcmUKPiBleGFjdGx5IHRoZSBzYW1lIGFzIHRoZSBvbmVz IG5lZWRlZCBvbiBJTEsrLCBzbyBqdXN0IHJldXNlIHRoZQo+IGZ1bmN0aW9uIHdlIGFscmVhZHkg aGF2ZS4KPgo+IHYyOiBJbnZlcnQgdGhlIHBhdGNoIG9yZGVyIHNvIHN0YWJsZSBiYWNrcG9ydHMg Z2V0IGVhc2llci4KClJlcGxpZWQgdG8gdGhlIG90aGVyIHNldCBmaXJzdC4uLiB0aGlzIG9yZGVy IGlzIGZpbmUgdG9vLCB3aXRoIG9yCndpdGhvdXQgY2M6IHN0YWJsZSBvbiB0aGUgb3RoZXIgb25l LgoKQlIsCkphbmkuCgoKPgo+IENjOiBzdGFibGVAdmdlci5rZXJuZWwub3JnCj4gU2lnbmVkLW9m Zi1ieTogUGF1bG8gWmFub25pIDxwYXVsby5yLnphbm9uaUBpbnRlbC5jb20+Cj4gLS0tCj4gIGRy aXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX3BtLmMgfCAxMiArKystLS0tLS0tLS0KPiAgMSBmaWxl IGNoYW5nZWQsIDMgaW5zZXJ0aW9ucygrKSwgOSBkZWxldGlvbnMoLSkKPgo+IGRpZmYgLS1naXQg YS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9wbS5jIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUv aW50ZWxfcG0uYwo+IGluZGV4IGZlNmMxYzYuLjAwMGIwMzMgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVy cy9ncHUvZHJtL2k5MTUvaW50ZWxfcG0uYwo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2lu dGVsX3BtLmMKPiBAQCAtMzQ3MCwxMiArMzQ3MCw2IEBAIHNrbF9hbGxvY2F0ZV9waXBlX2RkYihz dHJ1Y3QgaW50ZWxfY3J0Y19zdGF0ZSAqY3N0YXRlLAo+ICAJcmV0dXJuIDA7Cj4gIH0KPiAgCj4g LXN0YXRpYyB1aW50MzJfdCBza2xfcGlwZV9waXhlbF9yYXRlKGNvbnN0IHN0cnVjdCBpbnRlbF9j cnRjX3N0YXRlICpjb25maWcpCj4gLXsKPiAtCS8qIFRPRE86IFRha2UgaW50byBhY2NvdW50IHRo ZSBzY2FsZXJzIG9uY2Ugd2Ugc3VwcG9ydCB0aGVtICovCj4gLQlyZXR1cm4gY29uZmlnLT5iYXNl LmFkanVzdGVkX21vZGUuY3J0Y19jbG9jazsKPiAtfQo+IC0KPiAgLyoKPiAgICogVGhlIG1heCBs YXRlbmN5IHNob3VsZCBiZSAyNTcgKG1heCB0aGUgcHVuaXQgY2FuIGNvZGUgaXMgMjU1IGFuZCB3 ZSBhZGQgMnVzCj4gICAqIGZvciB0aGUgcmVhZCBsYXRlbmN5KSBhbmQgY3BwIHNob3VsZCBhbHdh eXMgYmUgPD0gOCwgc28gdGhhdAo+IEBAIC0zNTI2LDcgKzM1MjAsNyBAQCBzdGF0aWMgdWludDMy X3Qgc2tsX2FkanVzdGVkX3BsYW5lX3BpeGVsX3JhdGUoY29uc3Qgc3RydWN0IGludGVsX2NydGNf c3RhdGUgKmNzdAo+ICAJICogQWRqdXN0ZWQgcGxhbmUgcGl4ZWwgcmF0ZSBpcyBqdXN0IHRoZSBw aXBlJ3MgYWRqdXN0ZWQgcGl4ZWwgcmF0ZQo+ICAJICogd2l0aCBhZGRpdGlvbmFsIGFkanVzdG1l bnRzIGZvciBwbGFuZS1zcGVjaWZpYyBzY2FsaW5nLgo+ICAJICovCj4gLQlhZGp1c3RlZF9waXhl bF9yYXRlID0gc2tsX3BpcGVfcGl4ZWxfcmF0ZShjc3RhdGUpOwo+ICsJYWRqdXN0ZWRfcGl4ZWxf cmF0ZSA9IGlsa19waXBlX3BpeGVsX3JhdGUoY3N0YXRlKTsKPiAgCWRvd25zY2FsZV9hbW91bnQg PSBza2xfcGxhbmVfZG93bnNjYWxlX2Ftb3VudChwc3RhdGUpOwo+ICAKPiAgCXBpeGVsX3JhdGUg PSBhZGp1c3RlZF9waXhlbF9yYXRlICogZG93bnNjYWxlX2Ftb3VudCA+PiAxNjsKPiBAQCAtMzc0 MiwxMSArMzczNiwxMSBAQCBza2xfY29tcHV0ZV9saW5ldGltZV93bShzdHJ1Y3QgaW50ZWxfY3J0 Y19zdGF0ZSAqY3N0YXRlKQo+ICAJaWYgKCFjc3RhdGUtPmJhc2UuYWN0aXZlKQo+ICAJCXJldHVy biAwOwo+ICAKPiAtCWlmIChXQVJOX09OKHNrbF9waXBlX3BpeGVsX3JhdGUoY3N0YXRlKSA9PSAw KSkKPiArCWlmIChXQVJOX09OKGlsa19waXBlX3BpeGVsX3JhdGUoY3N0YXRlKSA9PSAwKSkKPiAg CQlyZXR1cm4gMDsKPiAgCj4gIAlyZXR1cm4gRElWX1JPVU5EX1VQKDggKiBjc3RhdGUtPmJhc2Uu YWRqdXN0ZWRfbW9kZS5jcnRjX2h0b3RhbCAqIDEwMDAsCj4gLQkJCSAgICBza2xfcGlwZV9waXhl bF9yYXRlKGNzdGF0ZSkpOwo+ICsJCQkgICAgaWxrX3BpcGVfcGl4ZWxfcmF0ZShjc3RhdGUpKTsK PiAgfQo+ICAKPiAgc3RhdGljIHZvaWQgc2tsX2NvbXB1dGVfdHJhbnNpdGlvbl93bShzdHJ1Y3Qg aW50ZWxfY3J0Y19zdGF0ZSAqY3N0YXRlLAoKLS0gCkphbmkgTmlrdWxhLCBJbnRlbCBPcGVuIFNv dXJjZSBUZWNobm9sb2d5IENlbnRlcgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fXwpJbnRlbC1nZnggbWFpbGluZyBsaXN0CkludGVsLWdmeEBsaXN0cy5mcmVl ZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5m by9pbnRlbC1nZngK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com ([192.55.52.93]:46602 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751033AbcJJJEl (ORCPT ); Mon, 10 Oct 2016 05:04:41 -0400 From: Jani Nikula To: Paulo Zanoni , intel-gfx@lists.freedesktop.org Cc: dhinakaran.pandiyan@intel.com, stable@vger.kernel.org, Paulo Zanoni Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/gen9: fix watermarks when using the pipe scaler In-Reply-To: <1475872138-16194-1-git-send-email-paulo.r.zanoni@intel.com> References: <1475872138-16194-1-git-send-email-paulo.r.zanoni@intel.com> Date: Mon, 10 Oct 2016 12:01:35 +0300 Message-ID: <8737k4tw5s.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: stable-owner@vger.kernel.org List-ID: On Fri, 07 Oct 2016, Paulo Zanoni wrote: > Luckily, the necessary adjustments for when we're using the scaler are > exactly the same as the ones needed on ILK+, so just reuse the > function we already have. > > v2: Invert the patch order so stable backports get easier. Replied to the other set first... this order is fine too, with or without cc: stable on the other one. BR, Jani. > > Cc: stable@vger.kernel.org > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_pm.c | 12 +++--------- > 1 file changed, 3 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index fe6c1c6..000b033 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3470,12 +3470,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, > return 0; > } > > -static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) > -{ > - /* TODO: Take into account the scalers once we support them */ > - return config->base.adjusted_mode.crtc_clock; > -} > - > /* > * The max latency should be 257 (max the punit can code is 255 and we add 2us > * for the read latency) and cpp should always be <= 8, so that > @@ -3526,7 +3520,7 @@ static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cst > * Adjusted plane pixel rate is just the pipe's adjusted pixel rate > * with additional adjustments for plane-specific scaling. > */ > - adjusted_pixel_rate = skl_pipe_pixel_rate(cstate); > + adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate); > downscale_amount = skl_plane_downscale_amount(pstate); > > pixel_rate = adjusted_pixel_rate * downscale_amount >> 16; > @@ -3742,11 +3736,11 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate) > if (!cstate->base.active) > return 0; > > - if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0)) > + if (WARN_ON(ilk_pipe_pixel_rate(cstate) == 0)) > return 0; > > return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000, > - skl_pipe_pixel_rate(cstate)); > + ilk_pipe_pixel_rate(cstate)); > } > > static void skl_compute_transition_wm(struct intel_crtc_state *cstate, -- Jani Nikula, Intel Open Source Technology Center