From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH] drm/i915: Limit the number of loops for reading a split 64bit register Date: Tue, 08 Sep 2015 15:36:32 +0300 Message-ID: <8737ypnl4f.fsf@intel.com> References: <1441697059-26221-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 026836E86A for ; Tue, 8 Sep 2015 05:33:22 -0700 (PDT) In-Reply-To: <1441697059-26221-1-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson , intel-gfx@lists.freedesktop.org Cc: Daniel Vetter , stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org T24gVHVlLCAwOCBTZXAgMjAxNSwgQ2hyaXMgV2lsc29uIDxjaHJpc0BjaHJpcy13aWxzb24uY28u dWs+IHdyb3RlOgo+IEluIEk5MTVfUkVBRDY0XzJ4MzIgd2UgYXR0ZW1wdCB0byByZWFkIGEgNjRi aXQgcmVnaXN0ZXIgdXNpbmcgMiAzMmJpdAo+IHJlYWRzLiBEdWUgdG8gdGhlIG5hdHVyZSBvZiB0 aGUgcmVnaXN0ZXJzIHdlIHRyeSB0byByZWFkIGluIHRoaXMgbWFubmVyLAo+IHRoZXkgbWF5IGlu Y3JlbWVudCBiZXR3ZWVuIHRoZSB0d28gaW5zdHJ1Y3Rpb24gKGUuZy4gYSB0aW1lc3RhbXAKPiBj b3VudGVyKS4gVG8ga2VlcCB0aGUgcmVzdWx0IGFjY3VyYXRlLCB3ZSByZXBlYXQgdGhlIHJlYWQg aWYgd2UgZGV0ZWN0Cj4gYW4gb3ZlcmZsb3cgKGkuZS4gdGhlIHVwcGVyIHZhbHVlIHZhcmllcyku IEhvd2V2ZXIsIHNvbWUgaGFyd2FyZSBpcyBqdXN0Cj4gcGxhaW4gZmxha3kgYW5kIG1heSBlbmRs ZXNzIGxvb3AgYXMgdGhlIHRoZSB1cHBlciAzMmJpdHMgYXJlIG5vdCBzdGFibGUuCj4gSnVzdCBn aXZlIHVwIGFmdGVyIGEgY291cGxlIG9mIHRyaWVzIGFuZCByZXBvcnQgd2hhdGV2ZXIgd2UgcmVh ZCBsYXN0Lgo+Cj4gUmVwb3J0ZWQtYnk6IHJ1c3NpYW5uZXVyb21hbmNlckB5YS5ydQo+IEJ1Z3pp bGxhOiBodHRwczovL2J1Z3MuZnJlZWRlc2t0b3Aub3JnL3Nob3dfYnVnLmNnaT9pZD05MTkwNgo+ IFNpZ25lZC1vZmYtYnk6IENocmlzIFdpbHNvbiA8Y2hyaXNAY2hyaXMtd2lsc29uLmNvLnVrPgo+ IENjOiBNaWNoYcWCIFdpbmlhcnNraSA8bWljaGFsLndpbmlhcnNraUBpbnRlbC5jb20+Cj4gQ2M6 IERhbmllbCBWZXR0ZXIgPGRhbmllbC52ZXR0ZXJAZmZ3bGwuY2g+Cj4gQ2M6IHN0YWJsZUB2Z2Vy Lmtlcm5lbC5vcmcKPiAtLS0KPiAgZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9kcnYuaCB8IDQg KystLQo+ICAxIGZpbGUgY2hhbmdlZCwgMiBpbnNlcnRpb25zKCspLCAyIGRlbGV0aW9ucygtKQo+ Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfZHJ2LmggYi9kcml2ZXJz L2dwdS9kcm0vaTkxNS9pOTE1X2Rydi5oCj4gaW5kZXggMTI4NzAwNzNkNThmLi44OTQzZGNiNzI0 YTggMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9kcnYuaAo+ICsrKyBi L2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfZHJ2LmgKPiBAQCAtMzQwMiwxMyArMzQwMiwxMyBA QCBpbnQgaW50ZWxfZnJlcV9vcGNvZGUoc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2 LCBpbnQgdmFsKTsKPiAgI2RlZmluZSBJOTE1X1JFQUQ2NChyZWcpCWRldl9wcml2LT51bmNvcmUu ZnVuY3MubW1pb19yZWFkcShkZXZfcHJpdiwgKHJlZyksIHRydWUpCj4gIAo+ICAjZGVmaW5lIEk5 MTVfUkVBRDY0XzJ4MzIobG93ZXJfcmVnLCB1cHBlcl9yZWcpICh7CQkJXAo+IC0JdTMyIHVwcGVy LCBsb3dlciwgdG1wOwkJCQkJCVwKPiArCXUzMiB1cHBlciwgbG93ZXIsIHRtcCwgbG9vcCA9IDA7 CQkJCVwKPiAgCXRtcCA9IEk5MTVfUkVBRCh1cHBlcl9yZWcpOwkJCQkJXAo+ICAJZG8gewkJCQkJ CQkJXAo+ICAJCXVwcGVyID0gdG1wOwkJCQkJCVwKPiAgCQlsb3dlciA9IEk5MTVfUkVBRChsb3dl cl9yZWcpOwkJCQlcCj4gIAkJdG1wID0gSTkxNV9SRUFEKHVwcGVyX3JlZyk7CQkJCVwKPiAtCX0g d2hpbGUgKHVwcGVyICE9IHRtcCk7CQkJCQkJXAo+ICsJfSB3aGlsZSAodXBwZXIgIT0gdG1wICYm IGxvb3ArKyAhPSAyKTsJCQkJXAoKRG8geW91IHRoaW5rIGl0IG1hdHRlcnMgdGhhdCB5b3UnbGwg dGFrZSB0aGUgcHJldmlvdXMsIG5vdCB0aGUgbGFzdCwKdmFsdWUgd2hlbiB5b3UgZ2l2ZSB1cD8K CkJSLApKYW5pLgoKPiAgCSh1NjQpdXBwZXIgPDwgMzIgfCBsb3dlcjsgfSkKPiAgCj4gICNkZWZp bmUgUE9TVElOR19SRUFEKHJlZykJKHZvaWQpSTkxNV9SRUFEX05PVFJBQ0UocmVnKQo+IC0tIAo+ IDIuNS4xCj4KPiBfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f Xwo+IEludGVsLWdmeCBtYWlsaW5nIGxpc3QKPiBJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Au b3JnCj4gaHR0cDovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVs LWdmeAoKLS0gCkphbmkgTmlrdWxhLCBJbnRlbCBPcGVuIFNvdXJjZSBUZWNobm9sb2d5IENlbnRl cgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpJbnRlbC1n ZnggbWFpbGluZyBsaXN0CkludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cDovL2xp c3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdmeAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com ([134.134.136.65]:18054 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754356AbbIHMdX convert rfc822-to-8bit (ORCPT ); Tue, 8 Sep 2015 08:33:23 -0400 From: Jani Nikula To: Chris Wilson , intel-gfx@lists.freedesktop.org Cc: Daniel Vetter , stable@vger.kernel.org Subject: Re: [Intel-gfx] [PATCH] drm/i915: Limit the number of loops for reading a split 64bit register In-Reply-To: <1441697059-26221-1-git-send-email-chris@chris-wilson.co.uk> References: <1441697059-26221-1-git-send-email-chris@chris-wilson.co.uk> Date: Tue, 08 Sep 2015 15:36:32 +0300 Message-ID: <8737ypnl4f.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Sender: stable-owner@vger.kernel.org List-ID: On Tue, 08 Sep 2015, Chris Wilson wrote: > In I915_READ64_2x32 we attempt to read a 64bit register using 2 32bit > reads. Due to the nature of the registers we try to read in this manner, > they may increment between the two instruction (e.g. a timestamp > counter). To keep the result accurate, we repeat the read if we detect > an overflow (i.e. the upper value varies). However, some harware is just > plain flaky and may endless loop as the the upper 32bits are not stable. > Just give up after a couple of tries and report whatever we read last. > > Reported-by: russianneuromancer@ya.ru > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91906 > Signed-off-by: Chris Wilson > Cc: Michał Winiarski > Cc: Daniel Vetter > Cc: stable@vger.kernel.org > --- > drivers/gpu/drm/i915/i915_drv.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 12870073d58f..8943dcb724a8 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -3402,13 +3402,13 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); > #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) > > #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ > - u32 upper, lower, tmp; \ > + u32 upper, lower, tmp, loop = 0; \ > tmp = I915_READ(upper_reg); \ > do { \ > upper = tmp; \ > lower = I915_READ(lower_reg); \ > tmp = I915_READ(upper_reg); \ > - } while (upper != tmp); \ > + } while (upper != tmp && loop++ != 2); \ Do you think it matters that you'll take the previous, not the last, value when you give up? BR, Jani. > (u64)upper << 32 | lower; }) > > #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) > -- > 2.5.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center