From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH] drm/i915: apply the PCI_D0/D3 hibernation workaround everywhere on pre GEN6 Date: Wed, 01 Jul 2015 11:35:48 +0300 Message-ID: <873818w9zv.fsf@intel.com> References: <1435673207-23030-1-git-send-email-imre.deak@intel.com> <20150630172706.GA28262@amd> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 843D56EA8D for ; Wed, 1 Jul 2015 01:33:16 -0700 (PDT) In-Reply-To: <20150630172706.GA28262@amd> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Pavel Machek , Imre Deak Cc: Paul Bolle , Dirk Griesbach , Mikko Rapeli , intel-gfx@lists.freedesktop.org, "Rafael J. Wysocki" , stable@vger.kernel.org, Daniel Vetter , Ilya Tumaykin List-Id: intel-gfx@lists.freedesktop.org T24gVHVlLCAzMCBKdW4gMjAxNSwgUGF2ZWwgTWFjaGVrIDxwYXZlbEB1Y3cuY3o+IHdyb3RlOgo+ IEhpIQo+Cj4+IGNvbW1pdCBkYTJiYzFiOWRiMzM1MWFkZGQyOTNlNWI4Mjc1N2VmZTFmNzdlZDFk Cj4+IEF1dGhvcjogSW1yZSBEZWFrIDxpbXJlLmRlYWtAaW50ZWwuY29tPgo+PiBEYXRlOiAgIFRo dSBPY3QgMjMgMTk6MjM6MjYgMjAxNCArMDMwMAo+PiAKPj4gICAgIGRybS9pOTE1OiBhZGQgcG93 ZXJvZmZfbGF0ZSBoYW5kbGVyCj4+IAo+PiBpbnRyb2R1Y2VkIGEgcmVncmVzc2lvbiBvbiBvbGQg cGxhdGZvcm1zIGR1cmluZyBoaWJlcm5hdGlvbi4gQSB3b3JrYXJvdW5kIHdhcwo+PiBhZGRlZCBp bgo+PiAKPj4gY29tbWl0IGFiM2JlNzNmYTdiNDNmNGMzNjQ4Y2UyOWI1ZmQ2NDllYTU0ZDNhZGIK Pj4gQXV0aG9yOiBJbXJlIERlYWsgPGltcmUuZGVha0BpbnRlbC5jb20+Cj4+IERhdGU6ICAgTW9u IE1hciAyIDEzOjA0OjQxIDIwMTUgKzAyMDAKPj4gCj4+ICAgICBkcm0vaTkxNTogZ2VuNDogd29y ayBhcm91bmQgaGFuZyBkdXJpbmcgaGliZXJuYXRpb24KPj4gCj4+IHVzaW5nIGFuIGV4cGxpY2l0 IGJsYWNrbGlzdCBmb3IgdGhlIEdFTnMvQklPUyB2ZW5kb3JzIHdoZXJlIHRoZSBpc3N1ZSB3YXMK Pj4gcmVwb3J0ZWQuIExhdGVyIHRoZXJlIHdlIGhhZCByZXBvcnRzIG9mIHRoZSBzYW1lIGZhaWx1 cmUgb24gcGxhdGZvcm1zIG5vdCBvbgo+PiB0aGlzIGxpc3QuCj4+IAo+PiBUbyBteSBiZXN0IGtu b3dsZWRnZSB0aGUgY29ycmVjdCB0aGluZyB0byBkbyBpcyBzdGlsbCB0byBwdXQgdGhlIGRldmlj ZSB0byBQQ0kKPj4gRDMgc3RhdGUgZHVyaW5nIGhpYmVybmF0aW9uLCBzZWUgWzFdIGFuZCBbMl0g Zm9yIHRoZSByZWFzb25zLiBUaGlzCj4+IGFsc28gYWxpZ25zCj4KPiBIbW0sIHNvIHRoZSByZWFz b25zIGFjY29yZGluZyB0byB5b3UgYXJlOgo+Cj4+IC0gQUNQSSBtYW5kYXRlcyB0aGF0IHRoZSBP U1BNICh0aGUga2VybmVsIGluIG91ciBjYXNlKSBwdXRzIGFsbAo+PiAgIGRldmljZXMKPj4gICBp bnRvIEQzIHRoYXQgYXJlIG5vdCB3YWtlLXVwIHNvdXJjZXMgKGk5MTUgaXMgbm90KSAoS3Vkb3Mg dG8gVmlsbGUKPj4gICBmb3IKPj4gICBwb2ludGluZyB0aGlzIG91dCkKPgo+IENsZWFybHksIEJJ T1MgdmVuZG9ycyBkaWQgbm90IHJlYWQgdGhpcywgYW5kIHByZXR0eSBjbGVhcmx5IFdpbmRvd3MK PiBkbyBub3QgZm9sbG93IHRoZSBzcGVjcywgZWl0aGVyLiBUaGF0IG1lYW5zIHRoYXQgaXQgaXMg YmFkIGlkZWEgZm9yIHVzCj4gdG8gZm9sbG93IHRoZSBzcGVjcywgYW5kIHRyaWdnZXIgQklPUyBi dWdzLiAKPgo+PiAtIEVtYmVkZGVkIHBhbmVscyBoYXZlIGEgd2VsbCBkZWZpbmVkIHNodXRkb3du IHNlcXVlbmNlLiBXZSBkb24ndAo+PiAgIGhhdmUKPj4gICBhbnkgZ29vZCByZWFzb24gdG8gbm90 IGZvbGxvdyB0aGlzLCBpbiBmYWN0IGZvciBzb21lIHBhbmVscyB0aGUKPj4gICBzdWJzZXF1ZW50 IHJlaW5pdGlhbGl6YXRpb24gY291bGQgYmUgcHJvYmxlbWF0aWMgaW4gY2FzZSBvZiBhIGhhcmQK Pj4gICBwb3dlci1vZmYuIChUaGFua3MgdG8gSmFuaSBmb3IgdGhpcyBpbmZvKQo+Cj4gUGxlYXNl IGNpdGUgY29uY3JldGUgZXhhbXBsZS4gSSBoYXZlIHlldCB0byBzZWUgbWFjaGluZSB0aGF0IHdv dWxkIG5vdAo+IHBvd2VyIHVwIG9uIGZvcmNlZCBwb3dlciBkb3duLiBJbiBmYWN0LCBJIGFyZ3Vl IHRoYXQgc3VjaCBtYWNoaW5lCj4gd291bGQgYmUgdmVyeSBicm9rZW4sIGFuZCB0aGF0IHN1Y2gg bWFjaGluZSBkb2VzIG5vdCBleGlzdC4gV2hpbGUgd2UKPiBoYXZlIHRoZXNlIHJlYWwgbWFjaGlu ZXMgYnJva2VuOgoKSSB3YXMgb3JpZ2luYWxseSByZWZlcnJpbmcgdG8gcmVib290cywgd2hpY2gg bWlnaHQgbm90IGJlIGFwcGxpY2FibGUKaGVyZS4gQW55d2F5LCB3ZSBoYXZlIHRvIGdvIG91dCBv ZiBvdXIgd2F5IHRvIGhhbmRsZSB0aGF0IHByb3Blcmx5IGluCnNvbWUgY2FzZXM6Cgpjb21taXQg MDE1MjdiMzEyNzk5N2VmNjM3MGQ1YWQ0ZmEyNWQ5Njg0N2ZiZjEyYQpBdXRob3I6IENsaW50IFRh eWxvciA8Y2xpbnRvbi5hLnRheWxvckBpbnRlbC5jb20+CkRhdGU6ICAgTW9uIEp1bCA3IDEzOjAx OjQ2IDIwMTQgLTA3MDAKCiAgICBkcm0vaTkxNS92bHY6IFQxMiBlRFAgcGFuZWwgdGltaW5nIGVu Zm9yY2VtZW50IGR1cmluZyByZWJvb3QKCkJSLApKYW5pLgoKPgo+PiArCSAqIExlbm92byBUaGlu a3BhZCBYMzAxLCBYNjFzLCBYNjAsIFQ2MCwgWDQxCj4+ICsJICogRnVqaXRzdSBGU0MgUzcxMTAK Pj4gKwkgKiBBY2VyIEFzcGlyZSAxODMwVAo+Cj4gV2hhdCBtYWtlcyB5b3UgdGhpbmsgdGhhdCBC SU9TIHdyaXRlcnMgd2lsbCBkbyBzb21ldGhpbmcgZGlmZmVyZW50IGZvcgo+IEdlbjYrIGhhcmR3 YXJlPyBYMzAxIGlzIG5vdCB0aGF0IG9sZC4KPiAJCQkJCQkJCQlQYXZlbAo+IC0tIAo+IChlbmds aXNoKSBodHRwOi8vd3d3LmxpdmVqb3VybmFsLmNvbS9+cGF2ZWxtYWNoZWsKPiAoY2Vza3ksIHBp Y3R1cmVzKSBodHRwOi8vYXRyZXkua2FybGluLm1mZi5jdW5pLmN6L35wYXZlbC9waWN0dXJlL2hv cnNlcy9ibG9nLmh0bWwKCi0tIApKYW5pIE5pa3VsYSwgSW50ZWwgT3BlbiBTb3VyY2UgVGVjaG5v bG9neSBDZW50ZXIKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3Jn Cmh0dHA6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com ([192.55.52.115]:12234 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753263AbbGAIdQ (ORCPT ); Wed, 1 Jul 2015 04:33:16 -0400 From: Jani Nikula To: Pavel Machek , Imre Deak Cc: intel-gfx@lists.freedesktop.org, "Rafael J. Wysocki" , Ilya Tumaykin , Dirk Griesbach , Mikko Rapeli , Paul Bolle , Ville =?utf-8?B?U3lyasOkbMOk?= , Daniel Vetter , stable@vger.kernel.org Subject: Re: [PATCH] drm/i915: apply the PCI_D0/D3 hibernation workaround everywhere on pre GEN6 In-Reply-To: <20150630172706.GA28262@amd> References: <1435673207-23030-1-git-send-email-imre.deak@intel.com> <20150630172706.GA28262@amd> Date: Wed, 01 Jul 2015 11:35:48 +0300 Message-ID: <873818w9zv.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: stable-owner@vger.kernel.org List-ID: On Tue, 30 Jun 2015, Pavel Machek wrote: > Hi! > >> commit da2bc1b9db3351addd293e5b82757efe1f77ed1d >> Author: Imre Deak >> Date: Thu Oct 23 19:23:26 2014 +0300 >> >> drm/i915: add poweroff_late handler >> >> introduced a regression on old platforms during hibernation. A workaround was >> added in >> >> commit ab3be73fa7b43f4c3648ce29b5fd649ea54d3adb >> Author: Imre Deak >> Date: Mon Mar 2 13:04:41 2015 +0200 >> >> drm/i915: gen4: work around hang during hibernation >> >> using an explicit blacklist for the GENs/BIOS vendors where the issue was >> reported. Later there we had reports of the same failure on platforms not on >> this list. >> >> To my best knowledge the correct thing to do is still to put the device to PCI >> D3 state during hibernation, see [1] and [2] for the reasons. This >> also aligns > > Hmm, so the reasons according to you are: > >> - ACPI mandates that the OSPM (the kernel in our case) puts all >> devices >> into D3 that are not wake-up sources (i915 is not) (Kudos to Ville >> for >> pointing this out) > > Clearly, BIOS vendors did not read this, and pretty clearly Windows > do not follow the specs, either. That means that it is bad idea for us > to follow the specs, and trigger BIOS bugs. > >> - Embedded panels have a well defined shutdown sequence. We don't >> have >> any good reason to not follow this, in fact for some panels the >> subsequent reinitialization could be problematic in case of a hard >> power-off. (Thanks to Jani for this info) > > Please cite concrete example. I have yet to see machine that would not > power up on forced power down. In fact, I argue that such machine > would be very broken, and that such machine does not exist. While we > have these real machines broken: I was originally referring to reboots, which might not be applicable here. Anyway, we have to go out of our way to handle that properly in some cases: commit 01527b3127997ef6370d5ad4fa25d96847fbf12a Author: Clint Taylor Date: Mon Jul 7 13:01:46 2014 -0700 drm/i915/vlv: T12 eDP panel timing enforcement during reboot BR, Jani. > >> + * Lenovo Thinkpad X301, X61s, X60, T60, X41 >> + * Fujitsu FSC S7110 >> + * Acer Aspire 1830T > > What makes you think that BIOS writers will do something different for > Gen6+ hardware? X301 is not that old. > Pavel > -- > (english) http://www.livejournal.com/~pavelmachek > (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html -- Jani Nikula, Intel Open Source Technology Center