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 for ath10k@lists.infradead.org; Thu, 27 Feb 2014 15:49:15 +0000
From: Kalle Valo <kvalo@qca.qualcomm.com>
Subject: Missing memory barriers
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Date: Thu, 27 Feb 2014 17:48:46 +0200
In-Reply-To: <CAHqTa-2kUJ1hrc8c2Kqy+cGexPJdisTMuUTH8WQ5KqV9qURwMw@mail.gmail.com>
 (Avery Pennarun's message of "Sun, 9 Feb 2014 03:00:45 -0500")
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To: Avery Pennarun <apenwarr@gmail.com>
Cc: Adrian Chadd <adrian@freebsd.org>, "ath10k@lists.infradead.org" <ath10k@lists.infradead.org>

Hi Avery,

starting a new thread about memory barriers:

Avery Pennarun <apenwarr@gmail.com> writes:

> On Wed, Jan 29, 2014 at 9:41 PM, Avery Pennarun <apenwarr@gmail.com> wrote:
>
> - there are definitely some missing memory barriers in here; in a few
> cases you can clearly see a write getting done before the read that
> came before it.  Looking at the definitions for iowrite32 and
> ioread32, and for rmb() and wmb(), we can see that the use of rmb()
> and wmb() do not work properly (at least on ARM) when you care about
> the ordering between reads and writes.  However, I don't think this
> actually causes the problem.

Can you tell more about this, please? Did you find out where we are
actually doing it wrong?

-- 
Kalle Valo

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