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Thu, 25 Jun 2026 08:14:17 -0700 (PDT) Received: from draig.lan ([185.124.0.195]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4926543be74sm49706485e9.1.2026.06.25.08.14.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2026 08:14:16 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 6C4905F8E5; Thu, 25 Jun 2026 16:14:15 +0100 (BST) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Jim MacArthur Cc: qemu-devel@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Richard Henderson Subject: Re: [PATCH v2 6/6] tests/tcg/arm: Tests for new FPRCVT instructions In-Reply-To: <20260624-jmac-fprcvt-v2-6-dc6cf8e512b6@linaro.org> (Jim MacArthur's message of "Wed, 24 Jun 2026 14:37:30 +0100") References: <20260624-jmac-fprcvt-v2-0-dc6cf8e512b6@linaro.org> <20260624-jmac-fprcvt-v2-6-dc6cf8e512b6@linaro.org> User-Agent: mu4e 1.14.2; emacs 30.1 Date: Thu, 25 Jun 2026 16:14:15 +0100 Message-ID: <874iiqireg.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Jim MacArthur writes: > We autodetect the presence of FPRCVT in the test cross compiler, > which is a recent feature in GCC and not supported by many distros > yet. If this is in place, we compile the existing fcvt.c test with > an extra compiler flag which uses the new SIMD instructions; the > output from the test is unchanged. > > The existing [US]CVTF instructions do not have a test, so no new > tests are added for the SIMD versions. They have been tested manually > to check the new SIMD versions produce the same numerical results as > the existing versions. > > Signed-off-by: Jim MacArthur > --- > tests/tcg/aarch64/Makefile.target | 14 +++++++++++++- > tests/tcg/arm/fcvt.c | 7 +++++++ > 2 files changed, 20 insertions(+), 1 deletion(-) > > diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefi= le.target > index 6203ac9b51..32f2689273 100644 > --- a/tests/tcg/aarch64/Makefile.target > +++ b/tests/tcg/aarch64/Makefile.target > @@ -28,9 +28,21 @@ config-cc.mak: Makefile > $(call cc-option,-march=3Darmv8.5-a, CROSS_CC_HAS_ARMV= 8_5); \ > $(call cc-option,-mbranch-protection=3Dstandard, CROSS_CC_HAS_ARMV= 8_BTI); \ > $(call cc-option,-march=3Darmv8.5-a+memtag, CROSS_CC_HAS_ARMV= 8_MTE); \ > - $(call cc-option,-Wa$(COMMA)-march=3Darmv9-a+sme $$fnia, CROSS_AS_H= AS_ARMV9_SME)) 3> config-cc.mak > + $(call cc-option,-Wa$(COMMA)-march=3Darmv9-a+sme $$fnia, CROSS_AS_H= AS_ARMV9_SME); \ > + $(call cc-option,-march=3Darmv9-a+fprcvt, CROSS_CC_HAS_ARMV= 9_FPRCVT)) 3> config-cc.mak > -include config-cc.mak >=20=20 > +ifneq ($(CROSS_CC_HAS_ARMV9_FPRCVT),) > +AARCH64_TESTS +=3D fcvt-fprcvt > +fcvt-fprcvt: LDFLAGS +=3D -lm > +fcvt-fprcvt: CFLAGS +=3D $(CROSS_CC_HAS_ARMV9_FPRCVT) -DFPRCVT > +fcvt-fprcvt: fcvt.c > + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) > +run-fcvt-fprcvt: fcvt-fprcvt > + $(call run-test,$<,$(QEMU) $<) > + $(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref) > +endif > + > ifneq ($(CROSS_CC_HAS_ARMV8_2),) > AARCH64_TESTS +=3D dcpop > dcpop: CFLAGS +=3D $(CROSS_CC_HAS_ARMV8_2) > diff --git a/tests/tcg/arm/fcvt.c b/tests/tcg/arm/fcvt.c > index ecebbb0247..7c0cc4367e 100644 > --- a/tests/tcg/arm/fcvt.c > +++ b/tests/tcg/arm/fcvt.c > @@ -171,8 +171,14 @@ static void convert_single_to_integer(void) > #if defined(__arm__) > /* asm("vcvt.s32.f32 %s0, %s1" : "=3Dt" (output) : "t" (input));= */ > output =3D input; > +#else > +#ifdef FPRCVT > + asm("fcvtzs d0, %s1\r\n" > + "fmov %0, d0" : > + "=3Dr" (output) : "w" (input)); > #else > asm("fcvtzs %0, %s1" : "=3Dr" (output) : "w" (input)); > +#endif > #endif > print_int64(i, output); > } > @@ -425,6 +431,7 @@ int main(int argc, char *argv[argc]) > convert_double_to_integer(); > convert_half_to_integer(); >=20=20 > + > /* And now with ARM alternative FP16 */ > #if defined(__arm__) > asm("vmrs r1, fpscr\n\t" Ok with the following: --8<---------------cut here---------------start------------->8--- modified =EE=98=9E target/arm/tcg/translate-a64.c @@ -9882,6 +9882,9 @@ static bool do_cvtf_scalar(DisasContext *s, MemOp esz= , int rd, int shift, static bool do_cvtf_g(DisasContext *s, arg_fcvt *a, bool is_signed) { TCGv_i64 tcg_int; + g_assert(s->is_nonstreaming =3D=3D false); + + g_assert_not_reached(); int check =3D fp_access_check_scalar_hsd(s, a->esz); =20 if (check <=3D 0) { @@ -9917,6 +9920,10 @@ static bool do_cvtf_f(DisasContext *s, arg_fcvt *a, = MemOp src_mop_int, TCGv_i64 tcg_int; int check; =20 + g_assert(s->is_nonstreaming =3D=3D false); + + g_assert_not_reached(); + /* FEAT_FPRCVT allows vector forms in streaming mode */ if (dc_isar_feature(aa64_fprcvt, s)) { s->is_nonstreaming =3D false; @@ -10065,6 +10072,11 @@ static bool do_fcvt_simd(DisasContext *s, arg_fcvt= *a, ARMFPRounding rmode, bool is_signed) { TCGv_i64 tcg_int; + + g_assert(s->is_nonstreaming =3D=3D false); + + /* g_assert_not_reached(); */ + int check =3D fp_access_check_scalar_hsd(s, a->esz); =20 --8<---------------cut here---------------end--------------->8--- I could verify that do_fcvt_simd is called and is_nonstreaming is set by the "hidden" decode logic. However the other two cases don't get touched. What would we need to expand the test to them? --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro