From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 57DB0C4332F for ; Sat, 28 Oct 2023 18:19:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:References :In-Reply-To:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LfY9L2N8JLBtLtheXTrz5DKoCTbpWNIWE7RHqz9S1Ns=; b=JBZCBdMymeMgR+ 58usOxVrCmUYLe5cpUggEEDTSGf9LLgcmqbIwhFgMJT8guCpBDnINW/gCI122YShTid7Mki26e2VV npYUlmDVa4YQDlQtuOF3RUIPP+yLuW11brEDB+FgwnA5obJLrnEu8gdgDMdTRTobgeiYRg/Jpfh5z CQ10VFYbYbLdlXR3o5M7BH7KC1r4Ib0VQ7UsJ9RhMTnpnhW/V5HF7A8mlZyb3ayF7380m8uRYIsqN A1gloYjBiyPgLStVn7kmypdI+DNc+/+kA80SspIxoy6nBLF65ztjqAYeUw3cu/HLqyOkbQSmoOkFR HN3DD1GvEZkafjfxnFDA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qwntn-000jgi-0z; Sat, 28 Oct 2023 18:19:03 +0000 Received: from galois.linutronix.de ([2a0a:51c0:0:12e:550::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qwnti-000jei-2e for linux-riscv@lists.infradead.org; Sat, 28 Oct 2023 18:19:00 +0000 From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1698517132; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bBi3pGj4Mfcw1N6bhhpo3vAJXxk+culoWD3EB90gevc=; b=oS3DPgCWxr0nnSq3G0TD9jZvabasasK6Qjwj85o+PxwXbhoBBUtk2VRdK92arHm7c8VBe6 J0Qo5CoWDFlbZFioFFX4TWUWsFc//ln7YgKoDD57YKPe+COx33QRcKN7ROYw4fL4rr8nnS BjW6jatP4lvUf/jWYxsoKKr+hfPOE1T3+Mga/ezH/7/aXFocRU/bRsYY7H8FU6cHaxfzX4 L+PlrApckVk/jnBmEdUbOK/Vj4aigw0Ly3ZWyAL4ca+HHEJ+A9NkuD5dZ3MdGy9/9GLC7t x3aAEarJA2xF6eq6ChA0snS7enjGZZDOl/F9Url3LQjR+K4TrBcKs0GTK8Jm+g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1698517132; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bBi3pGj4Mfcw1N6bhhpo3vAJXxk+culoWD3EB90gevc=; b=GiK+tZOUfVa0f3orWpewRXpQYcWKoqKClDpo3vBIZrHL8HZhWK80myuyx1eqlxiaAN3/jX 2a1hyDgfDLxRUUDg== To: =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= , Anup Patel Subject: Re: [PATCH v11 07/14] irqchip: Add RISC-V incoming MSI controller early driver In-Reply-To: <87pm11wyvb.fsf@all.your.base.are.belong.to.us> References: <20231023172800.315343-1-apatel@ventanamicro.com> <20231023172800.315343-8-apatel@ventanamicro.com> <878r7srx04.fsf@all.your.base.are.belong.to.us> <875y2ug023.fsf@all.your.base.are.belong.to.us> <87pm11wyvb.fsf@all.your.base.are.belong.to.us> Date: Sat, 28 Oct 2023 20:18:52 +0200 Message-ID: <874jia1ugj.ffs@tglx> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231028_111859_210665_DECD5824 X-CRM114-Status: GOOD ( 27.86 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Conor Dooley , Saravana Kannan , Marc Zyngier , Anup Patel , Atish Patra , linux-kernel@vger.kernel.org, Rob Herring , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , linux-riscv@lists.infradead.org, Frank Rowand , Andrew Jones Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T24gVGh1LCBPY3QgMjYgMjAyMyBhdCAxMDo1MSwgQmrDtnJuIFTDtnBlbCB3cm90ZToKPj4+ID4+ ID4gKyAgICAgcmF3X3NwaW5fbG9ja19pcnFzYXZlKCZscHJpdi0+aWRzX2xvY2ssIGZsYWdzKTsK Pj4+ID4+ID4gKyAgICAgYml0bWFwX2NsZWFyKGxwcml2LT5pZHNfZW5hYmxlZF9iaXRtYXAsIHZl Yy0+bG9jYWxfaWQsIDEpOwo+Pj4gPj4gPiArICAgICByYXdfc3Bpbl91bmxvY2tfaXJxcmVzdG9y ZSgmbHByaXYtPmlkc19sb2NrLCBmbGFncyk7Cj4+PiA+PiA+ICsKPj4+ID4+ID4gKyAgICAgaW1z aWNfcmVtb3RlX3N5bmModmVjLT5jcHUpOwo+Pj4gPj4KPj4+ID4+IHg4NiBzZWVtcyB0byBzZXQg YSB0aW1lciBpbnN0ZWFkLCBmb3IgdGhlIHJlbW90ZSBjcHUgY2xlYW51cCwgd2hpY2ggY2FuCj4+ PiA+PiBiZSBtdWNoIGNoZWFwZXIsIGFuZCBsZXNzIGluIGluc3RydXNpdmUuIElzIHRoYXQgYXBw bGljYWJsZSBoZXJlPwo+Pj4gPgo+Pj4gPiBUaGUgaXNzdWUgd2l0aCB0aGF0IGFwcHJvYWNoIGlz IGRlY2lkaW5nIHRoZSByaWdodCBkdXJhdGlvbgo+Pj4gPiBvZiB0aW1lciBpbnRlcnJ1cHQuIFRo ZXJlIG1pZ2h0IGJlIHBsYXRmb3JtcyB3aG8gbmVlZAo+Pj4gPiBpbW1lZGlhdGUgbWFzay91bm1h c2sgcmVzcG9uc2UuIFdlIGNhbiBjZXJ0YWluZWx5Cj4+PiA+IGtlZXAgaW1wcm92aW5nL3R1bmlu ZyB0aGlzIG92ZXItdGltZS4KPj4+Cj4+PiBBbnkgY29uY3JldGUgZXhhbXBsZXMgd2hlcmUgdGhp cyBpcyBhbiBhY3R1YWwgcHJvYmxlbT8KPj4KPj4gRG8geW91IGhhdmUgYSBjb25jcmV0ZSB0aW1l ciBkdXJhdGlvbiB3aXRoIHByb3BlciBqdXN0aWZpY2F0aW9uID8KPgo+IEkgd291bGQgc2ltcGx5 IG1pbWljIHdoYXQgeDg2IGRvZXMgZm9yIG5vdyAtLSBqaWZmaWVzICsgMS4KClRoYXQncyBnb29k IGVub3VnaC4gVGhlIHBvaW50IGlzIHRoYXQgdGhlIGludGVycnVwdCBtaWdodCBzdGlsbCBlbmQg dXAKb24gdGhlIG9sZCB0YXJnZXQgQ1BVIGRlcGVuZGluZyBvbiB0aW1pbmcsIGJ1dCB0aGUgbmV4 dCBvbmUgaXMKZ3VhcmFudGVlZCB0byBiZSB0YXJnZXRlZCB0byB0aGUgbmV3IHRhcmdldCBDUFUu CgpTbyB5b3UgY2FuJ3QgY2xlYW51cCB0aGUgdmVjdG9yIG9uIHRoZSBvbGQgdGFyZ2V0IGltbWVk aWF0ZWx5LCBidXQgaXQKZG9lcyBub3QgbWF0dGVyIGF0IGFsbCB3aGV0aGVyIHlvdSBjbGVhbiBp dCB1cCAxMG1zIG9yIDEwcyBsYXRlci4gSXQncwpqdXN0IHdhc3RpbmcgYSB2ZWN0b3Igb24gdGhl IG9sZCB0YXJnZXQuCgpEb2luZyBpdCB3aXRoIGFuIElQSSAoYXMgeDg2IGRpZCBiZWZvcmUpIG9u bHkgd29ya3Mgd2hlbiB0aGUgSVBJIHZlY3RvcgppcyBvZiBsb3dlciBwcmlvcml0eSB0aGFuIHRo ZSB2ZWN0b3Igd2hpY2ggZ290IG1vdmVkLiBPdGhlcndpc2UgdGhlIElQSQp3aWxsIGJlIHNlcnZl ZCBmaXJzdCwgZmluZCB0aGUgdmVjdG9yIHBlbmRpbmcgYW5kIHRoZW4gaXQncyB1cCBhIGNyZWVr CndpdGhvdXQgYSBwYWRkbGUgYmVjYXVzZSBpdCBjYW4ndCByZXRyaWdnZXIgdGhlIElQSSBhcyB0 aGF0IHdvdWxkIGFnYWluCmJlIHNlcnZlZCBmaXJzdC4gU28gaXQgY2FuJ3QgY2xlYW4gdXAgZXZl ci4uLgoKVGhlIHRpbWVyIGp1c3QgYXZvaWRzIHRoaXMgYW5kIGFzIEkgc2FpZCB0aGUgZGVsYXkg aXMgY29tcGxldGVseQppcnJlbGV2YW50LgoKPj4+ID4+IFRoZSByZWFzb24gSSdtIGFza2luZyBp cyBiZWNhdXNlIEknbSBwcmV0dHkgY2VydGFpbiB0aGF0IHg4NiBoYXMgcHJvcGVyCj4+PiA+PiBN U0kgc3VwcG9ydCAoVGhvbWFzIEdsZWl4bmVyIGNhbiBhbnN3ZXIgZm9yIHN1cmUhIDstKSkKCkl0 IGhhcyBwcm9wZXIgTVNJIHN1cHBvcnQgd2l0aCBzb21lIGxpbWl0YXRpb25zLgoKPj4+ID4+IElN U0lDIHNtZWxscyBhIGxvdCBsaWtlIHRoZSB0aGUgTEFQSUMuCgpFZWV3LiA6KQoKPiBNeSBjbGFp bSBpcyB0aGF0IHg4NiBkb2VzIHN1cHBvcnQgbGVnYWN5LU1TSSwgYnV0IGZvciBkZXNpZ24gZGVj aXNpb24sCj4gaGFzIGF2b2lkZWQgbXVsdGktTVNJLgoKVGhlcmUgYXJlIHR3byB2YXJpYW50cyBv ZiBQQ0kvTVNJOgoKICAxKSBNU0kKICAyKSBNU0ktWAoKTmVpdGhlciBvZiB0aGVtIGlzIGxlZ2Fj eSBhbmQgYm90aCBzdXBwb3J0IG11bHRpcGxlIHZlY3RvcnMgYXQgdGhlCmRldmljZSBoYXJkd2Fy ZSBsZXZlbC4KCiAgIzEgTVNJCgogICAgICBBZmZpbml0eSBzZXR0aW5nIHJlcXVpcmVzIHRvIG1v dmUgYWxsIHZlY3RvcnMgdG8gdGhlIG5ldyB0YXJnZXQgaW4KICAgICAgb25lIGdvIGJlY2F1c2Ug dGhlIGRldmljZSBnZXRzIG9ubHkgdGhlIGJhc2UgdmVjdG9yIGluIHRoZSBNU0kKICAgICAgbWVz c2FnZSBhbmQgdXNlcyB0aGUgbG93ZXIgYml0cyBhcyBpbmRleC4KCiAgICAgIFNvIHRoYXQncyBv ZiBsaW1pdGVkIHVzZSBhbnl3YXkgYmVjYXVzZSBpdCdzIGltcG9zc2libGUgdG8gdXNlCiAgICAg IHRoYXQgZm9yIG11bHRpLXF1ZXVlIG9yIG90aGVyIHB1cnBvc2VzIHdoZXJlIHRoZSBtYWluIHBv aW50IGlzIHRvCiAgICAgIHNwcmVhZCB0aGUgaW50ZXJydXB0cyBhY2Nyb3NzIENQVXMuCgogICAg ICBJdCBkb2VzIG5vdCBoYXZlIG1hbmRhdG9yeSBtYXNraW5nIHdoaWNoIG1ha2VzIGFmZmluaXR5 IGNoYW5nZXMKICAgICAgZXZlbiBtb3JlIHByb2JsZW1hdGljIGF0IGxlYXN0IG9uIHg4NiBiZWNh dXNlIHRoZSB1cGRhdGUgdG8gdGhlCiAgICAgIG1lc3NhZ2Ugc3RvcmUgaW4gdGhlIFBDSSBjb25m aWcgc3BhY2UgaXMgbm9uLWF0b21pYy4gU2VlIHRoZSBkYW5jZQogICAgICB3aGljaCBpcyByZXF1 aXJlZCBmb3IgYSBzaW5nbGUgdmVjdG9yIGluIG1zaV9zZXRfYWZmaXR5KCkuCgogICAgICBJT1cs IGlmIHRoZSBNU0kgbWVzc2FnZSBpcyBkaXJlY3RseSBkZWxpdmVyZWQgdG8gdGhlIHRhcmdldCBD UFUKICAgICAgYW5kIHRoZSBkZXZpY2UgZG9lcyBub3Qgc3VwcG9ydCBtYXNraW5nIHRoZW4gc2lu Z2xlIHZlY3RvciBpcwogICAgICBhbHJlYWR5IGNvbXBsZXh0IGFuZCBtdWx0aS1NU0kgc3VwcG9y dCBiZWNvbWVzIGEgaG9ycm9yc2hvdy4KCiAgICAgIEFub3RoZXIgaXNzdWUgZXNwZWNpYWxseSBv biB4ODYgd2l0aCB0aGUgbGltaXRhdGlvbiBvZiBhYm91dCAyMDAKICAgICAgZGV2aWNlIHZlY3Rv cnMgcGVyIENQVSBpcyB0aGUgcmVxdWlyZW1lbnQgdG8gYWxsb2NhdGUgYQogICAgICBjb25zZWN1 dGl2ZSB2ZWN0b3Igc3BhY2UgcG93ZXIgb2YgMiBhbGlnbmVkLiBUaGF0J3MgcHJldHR5IGZhc3Qg YXQKICAgICAgdGhlIHBvaW50IG9mIHZlY3RvciBleGhhdXN0aW9uLgoKICAgICAgVGhhdCBfYXJl XyB0aGUgcmVhc29ucyB3aHkgWDg2IGRvZXMgbm90IHN1cHBvcnQgbXVsdGktTVNJIHdpdGhvdXQK ICAgICAgaW50ZXJydXB0IHJlbWFwcGluZy4gSXQganVzdCBkb2VzIHRoZSBvbmx5IHNhbmUgdGhp bmcgYW5kIGxpbWl0cwogICAgICB0byBvbmUgdmVjdG9yIHBlciBkZXZpY2UuCgogICAgICBJbnRl cnJ1cHQgcmVtYXBwaW5nIGF2b2lkcyB0aGUgcHJvYmxlbSBiZWNhdXNlIGl0IGFsbG93cyB0byBz dGVlcgogICAgICB0aGUgdmVjdG9ycyBpbmRpdmlkdWFsbHkgYW5kIHRoZSBhZmZpbml0eSB1cGRh dGUgaXMgYXRvbWljLiBJdAogICAgICBvYnZpb3VzbHkgYWxzbyBsaWZ0cyB0aGUgcmVxdWlyZW1l bnQgZm9yIGEgY29uc2VjdXRpdmUgdmVjdG9yCiAgICAgIHNwYWNlLgoKICAgICAgU2VyaW91bHN5 IHcvbyBpbnRlcnJ1cHQgcmVtYXBwaW5nIG9yIGFuIGVxdWl2YWxlbnQgdHJhbnNsYXRpb24KICAg ICAgbWVjaGFuaXNtIHdoaWNoIGFsbG93cyB0byBzdGVlciB0aGUgdmVjdG9ycyBpbmRpdmlkdWFs bHkgbXVsdGktTVNJCiAgICAgIGlzIGFic29sdXRlbHkgcG9pbnRsZXNzIGFuZCBub3Qgd29ydGgg dGhlIHRyb3VibGUgdG8gc3VwcG9ydCBpdC4KCgogICMyIE1TSS1YCgogICAgICAgSGFzIGEgbWVz c2FnZSBzdG9yZSBwZXIgdmVjdG9yIGFuZCBtYW5kYXRvcnkgcGVyIHZlY3RvciBtYXNraW5nCiAg ICAgICB3aGljaCBtYWtlcyBtdWx0aSB2ZWN0b3Igc3VwcG9ydCB0cml2aWFsIGV2ZW4gdy9vIGlu dGVycnVwdAogICAgICAgcmVtYXBwaW5nLiBJdCBkb2VzIG5laXRoZXIgcmVxdWlyZSBhIGNvbnNl Y3V0aXZlIHZlY3RvciBzcGFjZS4KClNvIGlmIEFJQSBpcyBzaW1pbGFyIHRvIHRoZSBBUElDLCB0 aGVuIHNpbmdsZSBNU0kgbmVlZHMgdGhlIHNhbWUgZGFuY2UKYW5kIG11bHRpLU1TSSBuZWVkcyB0 aGF0IHRoZWF0cmUgXiBOLgoKPiBBRkFJVSwgdGhlcmUgYXJlIGZldyBtdWx0aS1NU0kgZGV2aWNl cyBvdXQgdGhlcmUuCgpZb3Ugd2lzaC4gTVNJLVggaXMgIm1vcmUgZXhwZW5zaXZlIiAocHJvYmFs eSAwLjUgQ2VudCkuIE5vdyB0aGF0CmludGVycnVwdCByZW1hcHBpbmcgaXMgcHJldHR5IG11Y2gg YWx3YXlzIGF2YWlsYWJsZSBvbiB4ODYsIHRoZSBwcm9ibGVtCmlzICJmaXhlZCIgaW5kaXJlY3Rs eS4gU28gZXNwZWNpYWxseSB4ODYgb24tY2hpcCBkZXZpY2VzIHN0aWxsIHVzZSBNU0kKYW5kIG5v dCBNU0ktWC4gTVNJLVggaXMgcHJpbWFyaWx5IHVzZWQgaW4gbXVsdGktcXVldWUgZGV2aWNlcyBh cwptdWx0aS1NU0kgaXMgbGltaXRlZCB0byAzMiB2ZWN0b3JzLgoKVGhhbmtzLAoKICAgICAgICB0 Z2x4CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51 eC1yaXNjdiBtYWlsaW5nIGxpc3QKbGludXgtcmlzY3ZAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRw Oi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LXJpc2N2Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0A8D18027 for ; Sat, 28 Oct 2023 18:18:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="oS3DPgCW"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="GiK+tZOU" Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9858ED; Sat, 28 Oct 2023 11:18:54 -0700 (PDT) From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1698517132; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bBi3pGj4Mfcw1N6bhhpo3vAJXxk+culoWD3EB90gevc=; b=oS3DPgCWxr0nnSq3G0TD9jZvabasasK6Qjwj85o+PxwXbhoBBUtk2VRdK92arHm7c8VBe6 J0Qo5CoWDFlbZFioFFX4TWUWsFc//ln7YgKoDD57YKPe+COx33QRcKN7ROYw4fL4rr8nnS BjW6jatP4lvUf/jWYxsoKKr+hfPOE1T3+Mga/ezH/7/aXFocRU/bRsYY7H8FU6cHaxfzX4 L+PlrApckVk/jnBmEdUbOK/Vj4aigw0Ly3ZWyAL4ca+HHEJ+A9NkuD5dZ3MdGy9/9GLC7t x3aAEarJA2xF6eq6ChA0snS7enjGZZDOl/F9Url3LQjR+K4TrBcKs0GTK8Jm+g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1698517132; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bBi3pGj4Mfcw1N6bhhpo3vAJXxk+culoWD3EB90gevc=; b=GiK+tZOUfVa0f3orWpewRXpQYcWKoqKClDpo3vBIZrHL8HZhWK80myuyx1eqlxiaAN3/jX 2a1hyDgfDLxRUUDg== To: =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= , Anup Patel Cc: Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley , Marc Zyngier , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v11 07/14] irqchip: Add RISC-V incoming MSI controller early driver In-Reply-To: <87pm11wyvb.fsf@all.your.base.are.belong.to.us> References: <20231023172800.315343-1-apatel@ventanamicro.com> <20231023172800.315343-8-apatel@ventanamicro.com> <878r7srx04.fsf@all.your.base.are.belong.to.us> <875y2ug023.fsf@all.your.base.are.belong.to.us> <87pm11wyvb.fsf@all.your.base.are.belong.to.us> Date: Sat, 28 Oct 2023 20:18:52 +0200 Message-ID: <874jia1ugj.ffs@tglx> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Thu, Oct 26 2023 at 10:51, Bj=C3=B6rn T=C3=B6pel wrote: >>> >> > + raw_spin_lock_irqsave(&lpriv->ids_lock, flags); >>> >> > + bitmap_clear(lpriv->ids_enabled_bitmap, vec->local_id, 1); >>> >> > + raw_spin_unlock_irqrestore(&lpriv->ids_lock, flags); >>> >> > + >>> >> > + imsic_remote_sync(vec->cpu); >>> >> >>> >> x86 seems to set a timer instead, for the remote cpu cleanup, which = can >>> >> be much cheaper, and less in instrusive. Is that applicable here? >>> > >>> > The issue with that approach is deciding the right duration >>> > of timer interrupt. There might be platforms who need >>> > immediate mask/unmask response. We can certainely >>> > keep improving/tuning this over-time. >>> >>> Any concrete examples where this is an actual problem? >> >> Do you have a concrete timer duration with proper justification ? > > I would simply mimic what x86 does for now -- jiffies + 1. That's good enough. The point is that the interrupt might still end up on the old target CPU depending on timing, but the next one is guaranteed to be targeted to the new target CPU. So you can't cleanup the vector on the old target immediately, but it does not matter at all whether you clean it up 10ms or 10s later. It's just wasting a vector on the old target. Doing it with an IPI (as x86 did before) only works when the IPI vector is of lower priority than the vector which got moved. Otherwise the IPI will be served first, find the vector pending and then it's up a creek without a paddle because it can't retrigger the IPI as that would again be served first. So it can't clean up ever... The timer just avoids this and as I said the delay is completely irrelevant. >>> >> The reason I'm asking is because I'm pretty certain that x86 has pro= per >>> >> MSI support (Thomas Gleixner can answer for sure! ;-)) It has proper MSI support with some limitations. >>> >> IMSIC smells a lot like the the LAPIC. Eeew. :) > My claim is that x86 does support legacy-MSI, but for design decision, > has avoided multi-MSI. There are two variants of PCI/MSI: 1) MSI 2) MSI-X Neither of them is legacy and both support multiple vectors at the device hardware level. #1 MSI Affinity setting requires to move all vectors to the new target in one go because the device gets only the base vector in the MSI message and uses the lower bits as index. So that's of limited use anyway because it's impossible to use that for multi-queue or other purposes where the main point is to spread the interrupts accross CPUs. It does not have mandatory masking which makes affinity changes even more problematic at least on x86 because the update to the message store in the PCI config space is non-atomic. See the dance which is required for a single vector in msi_set_affity(). IOW, if the MSI message is directly delivered to the target CPU and the device does not support masking then single vector is already complext and multi-MSI support becomes a horrorshow. Another issue especially on x86 with the limitation of about 200 device vectors per CPU is the requirement to allocate a consecutive vector space power of 2 aligned. That's pretty fast at the point of vector exhaustion. That _are_ the reasons why X86 does not support multi-MSI without interrupt remapping. It just does the only sane thing and limits to one vector per device. Interrupt remapping avoids the problem because it allows to steer the vectors individually and the affinity update is atomic. It obviously also lifts the requirement for a consecutive vector space. Serioulsy w/o interrupt remapping or an equivalent translation mechanism which allows to steer the vectors individually multi-MSI is absolutely pointless and not worth the trouble to support it. #2 MSI-X Has a message store per vector and mandatory per vector masking which makes multi vector support trivial even w/o interrupt remapping. It does neither require a consecutive vector space. So if AIA is similar to the APIC, then single MSI needs the same dance and multi-MSI needs that theatre ^ N. > AFAIU, there are few multi-MSI devices out there. You wish. MSI-X is "more expensive" (probaly 0.5 Cent). Now that interrupt remapping is pretty much always available on x86, the problem is "fixed" indirectly. So especially x86 on-chip devices still use MSI and not MSI-X. MSI-X is primarily used in multi-queue devices as multi-MSI is limited to 32 vectors. Thanks, tglx