From: Jani Nikula <jani.nikula@linux.intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>,
intel-xe@lists.freedesktop.org
Cc: Matt Roper <matthew.d.roper@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>
Subject: Re: [Intel-xe] [PATCH v5 12/21] drm/xe: Add support for OOB workarounds
Date: Tue, 29 Aug 2023 12:49:14 +0300 [thread overview]
Message-ID: <874jki2n6t.fsf@intel.com> (raw)
In-Reply-To: <20230526164358.86393-13-lucas.demarchi@intel.com>
On Fri, 26 May 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index d703dc0f7b21..d9906f326d38 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -9,6 +9,7 @@
> #include <kunit/visibility.h>
> #include <linux/compiler_types.h>
>
> +#include "generated/xe_wa_oob.h"
> #include "regs/xe_engine_regs.h"
> #include "regs/xe_gt_regs.h"
> #include "regs/xe_regs.h"
> @@ -73,8 +74,8 @@
> * engine registers are restored in a context restore sequence. This is
> * currently not used in the driver.
> *
> - * - Other: There are WAs that, due to their nature, cannot be applied from a
> - * central place. Those are peppered around the rest of the code, as needed.
> + * - Other/OOB: There are WAs that, due to their nature, cannot be applied from
> + * a central place. Those are peppered around the rest of the code, as needed.
> * Workarounds related to the display IP are the main example.
> *
> * .. [1] Technically, some registers are powercontext saved & restored, so they
> @@ -579,8 +580,31 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
> {}
> };
>
> +static __maybe_unused const struct xe_rtp_entry oob_was[] = {
> +#include <generated/xe_wa_oob.c>
This should use "generated/xe_wa_oob.c" i.e. not system header
inclusion.
I might even have used some other subdir name to avoid the conflict with
include/generated.
BR,
Jani.
> + {}
> +};
> +
> +static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);
> +
> __diag_pop();
>
> +/**
> + * xe_wa_process_oob - process OOB workaround table
> + * @gt: GT instance to process workarounds for
> + *
> + * Process OOB workaround table for this platform, marking in @gt the
> + * workarounds that are active.
> + */
> +void xe_wa_process_oob(struct xe_gt *gt)
> +{
> + struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
> +
> + xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob,
> + ARRAY_SIZE(oob_was));
> + xe_rtp_process(&ctx, oob_was);
> +}
> +
> /**
> * xe_wa_process_gt - process GT workaround table
> * @gt: GT instance to process workarounds for
> @@ -641,13 +665,14 @@ void xe_wa_process_lrc(struct xe_hw_engine *hwe)
> int xe_wa_init(struct xe_gt *gt)
> {
> struct xe_device *xe = gt_to_xe(gt);
> - size_t n_lrc, n_engine, n_gt, total;
> + size_t n_oob, n_lrc, n_engine, n_gt, total;
> unsigned long *p;
>
> n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was));
> n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was));
> n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was));
> - total = n_gt + n_engine + n_lrc;
> + n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was));
> + total = n_gt + n_engine + n_lrc + n_oob;
>
> p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
> if (!p)
> @@ -658,6 +683,8 @@ int xe_wa_init(struct xe_gt *gt)
> gt->wa_active.engine = p;
> p += n_engine;
> gt->wa_active.lrc = p;
> + p += n_lrc;
> + gt->wa_active.oob = p;
>
> return 0;
> }
> @@ -677,4 +704,9 @@ void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p)
> drm_printf(p, "\nLRC Workarounds\n");
> for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was))
> drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name);
> +
> + drm_printf(p, "\nOOB Workarounds\n");
> + for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was))
> + if (oob_was[idx].name)
> + drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);
> }
> diff --git a/drivers/gpu/drm/xe/xe_wa.h b/drivers/gpu/drm/xe/xe_wa.h
> index defefa5d9611..cfe685989524 100644
> --- a/drivers/gpu/drm/xe/xe_wa.h
> +++ b/drivers/gpu/drm/xe/xe_wa.h
> @@ -11,6 +11,7 @@ struct xe_gt;
> struct xe_hw_engine;
>
> int xe_wa_init(struct xe_gt *gt);
> +void xe_wa_process_oob(struct xe_gt *gt);
> void xe_wa_process_gt(struct xe_gt *gt);
> void xe_wa_process_engine(struct xe_hw_engine *hwe);
> void xe_wa_process_lrc(struct xe_hw_engine *hwe);
> @@ -18,4 +19,12 @@ void xe_wa_process_lrc(struct xe_hw_engine *hwe);
> void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe);
> void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p);
>
> +/**
> + * XE_WA - Out-of-band workarounds, that don't fit the lifecycle any
> + * other more specific type
> + * @gt__: gt instance
> + * @id__: XE_OOB_<id__>, as generated by build system in generated/xe_wa_oob.h
> + */
> +#define XE_WA(gt__, id__) test_bit(XE_WA_OOB_ ## id__, (gt__)->wa_active.oob)
> +
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> new file mode 100644
> index 000000000000..e69de29bb2d1
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2023-08-29 9:49 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-26 16:43 [Intel-xe] [PATCH v5 00/21] Dump + OOB workarounds Lucas De Marchi
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 01/21] drm/xe: Fix Wa_22011802037 annotation Lucas De Marchi
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 02/21] drm/xe/rtp: Split rtp process initialization Lucas De Marchi
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 03/21] drm/xe/rtp: Replace XE_WARN_ON Lucas De Marchi
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 04/21] drm/xe/rtp: Add "_sr" to entry/function names Lucas De Marchi
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 05/21] drm/xe/rtp: Allow to track active workarounds Lucas De Marchi
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 06/21] drm/xe/wa: Track gt/engine/lrc " Lucas De Marchi
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 07/21] drm/xe/debugfs: Dump " Lucas De Marchi
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 08/21] drm/xe/rtp: Rename STEP to GRAPHICS_STEP Lucas De Marchi
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 09/21] drm/xe/rtp: Add check for media stepping Lucas De Marchi
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 10/21] drm/xe/rtp: Add support for entries with no action Lucas De Marchi
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 11/21] drm/xe: Include build directory Lucas De Marchi
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 12/21] drm/xe: Add support for OOB workarounds Lucas De Marchi
2023-08-29 9:49 ` Jani Nikula [this message]
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 13/21] drm/xe/guc: Port Wa_22012773006 to xe_wa Lucas De Marchi
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 14/21] drm/xe/guc: Port Wa_16011759253 " Lucas De Marchi
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 15/21] drm/xe/guc: Port Wa_14012197797/Wa_22011391025 " Lucas De Marchi
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 16/21] drm/xe/guc: Port Wa_16011777198 " Lucas De Marchi
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 17/21] drm/xe/guc: Port Wa_22012727170/Wa_22012727685 " Lucas De Marchi
2023-05-26 16:54 ` Matt Roper
2023-05-26 17:23 ` Lucas De Marchi
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 18/21] drm/xe/guc: Port Wa_16015675438/Wa_18020744125 " Lucas De Marchi
2023-05-26 16:56 ` Matt Roper
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 19/21] drm/xe/guc: Port Wa_1509372804 " Lucas De Marchi
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 20/21] drm/xe/rtp: Also check gt type Lucas De Marchi
2023-05-26 16:43 ` [Intel-xe] [PATCH v5 21/21] drm/xe/guc: Port Wa_14014475959 to xe_wa and fix it Lucas De Marchi
2023-05-26 16:58 ` [Intel-xe] ✓ CI.Patch_applied: success for Dump + OOB workarounds Patchwork
2023-05-26 17:00 ` [Intel-xe] ✓ CI.KUnit: " Patchwork
2023-05-26 17:04 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-05-26 17:32 ` [Intel-xe] ○ CI.BAT: info " Patchwork
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