From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 882FAECAAD3 for ; Wed, 31 Aug 2022 08:32:27 +0000 (UTC) Received: from localhost ([::1]:51810 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTJ98-0000V5-Jp for qemu-devel@archiver.kernel.org; Wed, 31 Aug 2022 04:32:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49470) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTJ7Z-0008At-ID for qemu-devel@nongnu.org; Wed, 31 Aug 2022 04:30:50 -0400 Received: from hsmtpd-def.xspmail.jp ([202.238.198.245]:58544) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTJ7V-0005wF-SF for qemu-devel@nongnu.org; Wed, 31 Aug 2022 04:30:49 -0400 X-Country-Code: JP Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by hsmtpd-out-0.asahinet.cluster.xspmail.jp (Halon) with ESMTPA id 155de646-c144-4164-aa5c-89b238251017; Wed, 31 Aug 2022 17:30:41 +0900 (JST) Received: from SIOS1075.ysato.ml (ae222174.dynamic.ppp.asahi-net.or.jp [14.3.222.174]) by sakura.ysato.name (Postfix) with ESMTPSA id B4ACF1C01B6; Wed, 31 Aug 2022 17:30:39 +0900 (JST) Date: Wed, 31 Aug 2022 17:30:37 +0900 Message-ID: <874jxsddci.wl-ysato@users.sourceforge.jp> From: Yoshinori Sato To: Richard Henderson Cc: BALATON Zoltan , qemu-devel@nongnu.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Subject: Re: [PATCH] target/sh4: Fix TB_FLAG_UNALIGN In-Reply-To: References: <20220829021325.154978-1-richard.henderson@linaro.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Received-SPF: softfail client-ip=202.238.198.245; envelope-from=ysato@users.sourceforge.jp; helo=hsmtpd-def.xspmail.jp X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, 30 Aug 2022 01:10:29 +0900, Richard Henderson wrote: >=20 > On 8/29/22 02:05, BALATON Zoltan wrote: > > On Sun, 28 Aug 2022, Richard Henderson wrote: > >> The value previously chosen overlaps GUSA_MASK. > >>=20 > >> Cc: qemu-stable@nongnu.org > >> Fixes: 4da06fb3062 ("target/sh4: Implement prctl_unalign_sigbus") > >> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/856 > >> Signed-off-by: Richard Henderson > >> --- > >> target/sh4/cpu.h | 2 +- > >> 1 file changed, 1 insertion(+), 1 deletion(-) > >>=20 > >> diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h > >> index 9f15ef913c..e79cbc59e2 100644 > >> --- a/target/sh4/cpu.h > >> +++ b/target/sh4/cpu.h > >> @@ -84,7 +84,7 @@ > >> #define DELAY_SLOT_RTE=A0=A0=A0=A0=A0=A0=A0=A0 (1 << 2) > >>=20 > >> #define TB_FLAG_PENDING_MOVCA=A0 (1 << 3) > >> -#define TB_FLAG_UNALIGN=A0=A0=A0=A0=A0=A0=A0 (1 << 4) > >> +#define TB_FLAG_UNALIGN=A0=A0=A0=A0=A0=A0=A0 (1 << 13) > >=20 > > Is it worth a comment to note why that value to avoid the same > > problem if another flag is added in the future? >=20 > Hmm, or perhaps move it down below, so that we see bit 3 used, then bits = 4-12, then bit 13. >=20 >=20 > r~ How about this fix? =46rom 69fc46c0e439026cabedc8ddfa0a880d0df09a6b Mon Sep 17 00:00:00 2001 From: Yoshinori Sato Date: Wed, 31 Aug 2022 17:12:59 +0900 Subject: [PATCH] sh4: cleanup for flags definition. Fix conflict TB_FLAG_UNALIGN and GUSA field. Add comment for gUSA operations. Signed-off-by: Yoshinori Sato --- target/sh4/cpu.h | 9 +++++++-- target/sh4/translate.c | 5 ++++- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 9f15ef913c..91810fda9b 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -86,9 +86,14 @@ #define TB_FLAG_PENDING_MOVCA (1 << 3) #define TB_FLAG_UNALIGN (1 << 4) =20 -#define GUSA_SHIFT 4 #ifdef CONFIG_USER_ONLY -#define GUSA_EXCLUSIVE (1 << 12) +/* gUSA information field in CPUArchState.flags */ +/* + b16 - b23: Exclusive region range (negative) + b24: pc in exclusive region flag (use normal decode) +*/ +#define GUSA_SHIFT 16 +#define GUSA_EXCLUSIVE (1 << 24) #define GUSA_MASK ((0xff << GUSA_SHIFT) | GUSA_EXCLUSIVE) #else /* Provide dummy versions of the above to allow tests against tbflags diff --git a/target/sh4/translate.c b/target/sh4/translate.c index f1b190e7cf..1d79a0721b 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -516,7 +516,7 @@ static void _decode_opc(DisasContext * ctx) /* Detect the start of a gUSA region. If so, update envflags and end the TB. This will allow us to see the end of the region (stored in R0) in the next TB. */ - if (B11_8 =3D=3D 15 && B7_0s < 0 && + if (B11_8 =3D=3D 15 && B7_0s < 0 && /* mov #-xxx, r15 */ (tb_cflags(ctx->base.tb) & CF_PARALLEL)) { ctx->envflags =3D deposit32(ctx->envflags, GUSA_SHIFT, 8, B7_0= s); ctx->base.is_jmp =3D DISAS_STOP; @@ -2267,7 +2267,9 @@ static void sh4_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) (tbflags & (1 << SR_RB))) * 0x10; ctx->fbank =3D tbflags & FPSCR_FR ? 0x10 : 0; =20 +#ifdef CONFIG_USER_ONLY if (tbflags & GUSA_MASK) { + /* In gUSA exclusive region */ uint32_t pc =3D ctx->base.pc_next; uint32_t pc_end =3D ctx->base.tb->cs_base; int backup =3D sextract32(ctx->tbflags, GUSA_SHIFT, 8); @@ -2285,6 +2287,7 @@ static void sh4_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) return; } } +#endif =20 /* Since the ISA is fixed-width, we can bound by the number of instructions remaining on the page. */ --=20 2.30.2 --=20 Yosinori Sato