Re: Why QEMU translates one instruction to a TB？

["Alex Bennée" <alex.bennee@linaro.org>]

casmac <climber.cui@qq.com> writes:

> Hi all, 
> &nbsp;&nbsp; &nbsp; We try to add DSP architecure to QEMU 4.2. To load the  COFF format object file, we have added loader code to load content from 
> &nbsp;  the object file. The rom_add_blob() function is used. We firstly  analyze the COFF file to figure out which sections are chained
> &nbsp; together(so each chain forms a "memory blob"), and then allocate the memory blobs. 
> &nbsp; 
> &nbsp; The psuedo code looks like:
> &nbsp; 
> &nbsp;&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; for(i=0; i<BADTYPE; i++){
> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; if(ary_sect_chain[i].exist) &nbsp; //there is a chain of sections to allocate 
> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; {
> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; ary_sect_chain[i].mem_region = g_new(MemoryRegion, 1);
> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; memory_region_init_ram(...);
> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; memory_region_add_subregion(sysmem, ....);
> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; rom_add_blob(....);
> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; }
> &nbsp; &nbsp; &nbsp;&nbsp; &nbsp; }
> &nbsp; 
<snip>

> &nbsp; &nbsp; if (unlikely(entry-&gt;addr_code &amp; TLB_MMIO)) {
> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; /* The region is not backed by
> RAM.&nbsp; */

This is the crux of it. If the address looked up isn't in a RAM region
then the TLB code can't assume a contiguous page of instructions or that
the instruction executed on one read will be the same on the next so it
will only execute a single instruction at a time and not cache the
resulting TB either forcing a fresh re-translation each time.

All TLB_MMIO access basically force the slow path.

I suspect there is something wrong in your memory region mappings.

-- 
Alex Bennée