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This +>> clock is optional because not all the SoCs using this IP need it but at +>> least for Armada 7K/8K it is actually mandatory. +>> +>> The binding documentation is updated accordingly. +>> +>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> +>> --- +>> Documentation/devicetree/bindings/pci/pci-armada8k.txt | 6 +++++- +>> drivers/pci/dwc/pcie-armada8k.c | 11 +++++++++++ +>> 2 files changed, 16 insertions(+), 1 deletion(-) +>> +>> diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt +>> index c1e4c3d10a74..9948b1e9a8e5 100644 +>> --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt +>> +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt +>> @@ -12,7 +12,11 @@ Required properties: +>> - "ctrl" for the control register region +>> - "config" for the config space region +>> - interrupts: Interrupt specifier for the PCIe controler +>> -- clocks: reference to the PCIe controller clock +>> +- clocks: reference to the PCIe controller clocks +>> +- clock-names: mandatory if there is a second clock, in this case the +>> + name must be "core" for the first clock and "reg" for the second +>> + one +>> + +> +> Unneeded new line added here. +will removed it + +> +>> +>> Example: +>> +>> diff --git a/drivers/pci/dwc/pcie-armada8k.c b/drivers/pci/dwc/pcie-armada8k.c +>> index f9b1aec25c5c..aa4e5cc4ab7b 100644 +>> --- a/drivers/pci/dwc/pcie-armada8k.c +>> +++ b/drivers/pci/dwc/pcie-armada8k.c +>> @@ -28,6 +28,7 @@ +>> struct armada8k_pcie { +>> struct dw_pcie *pci; +>> struct clk *clk; +>> + struct clk *clk_reg; +>> }; +>> +>> #define PCIE_VENDOR_REGS_OFFSET 0x8000 +>> @@ -229,6 +230,15 @@ static int armada8k_pcie_probe(struct platform_device *pdev) +>> if (ret) +>> return ret; +>> +>> + if (IS_ERR(pcie->clk_reg) && PTR_ERR(pcie->clk_reg) == -EPROBE_DEFER) { +>> + clk_disable_unprepare(pcie->clk); +>> + return -EPROBE_DEFER; +>> + } +>> + if (!IS_ERR(pcie->clk_reg)) { +>> + ret = clk_prepare_enable(pcie->clk_reg); +>> + if (ret) +>> + goto fail; +>> + } +>> /* Get the dw-pcie unit configuration/control registers base. */ +> +> Missing new line between the end of the block and the next comment. +> +OK + +> Regarding the error handling, doesn't it make more sense to also use a +> goto label to disable pcie->clk when getting the second clock gets a +> -EPROBE_DEFER ? +> +>> base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl"); +>> pci->dbi_base = devm_pci_remap_cfg_resource(dev, base); +>> @@ -247,6 +257,7 @@ static int armada8k_pcie_probe(struct platform_device *pdev) +>> return 0; +>> +>> fail: +>> + clk_disable_unprepare(pcie->clk_reg); +> +> So you are disabling/unpreparing the clock, which failed to +> prepare/enable ? + +I was thinking to a single user, in this case if the prepare/enable +failed then the disabling/unpreparing do nothing because the counter is +already to 0. But indeed in case of multiple users of the clock, then the +counter could be wrongly decrease. I will modify it by adding a other +label. + +Thanks, + +Gregory + +> +>> clk_disable_unprepare(pcie->clk); +>> +>> return ret; +> +> Thomas +> -- +> Thomas Petazzoni, CTO, Bootlin (formerly Free Electrons) +> Embedded Linux and Kernel engineering +> http://bootlin.com + +-- +Gregory Clement, Bootlin (formerly Free Electrons) +Embedded Linux and Kernel engineering +http://bootlin.com diff --git a/a/content_digest b/N1/content_digest index 5727c1b..9c3f7fd 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,93 +1,123 @@ "ref\020180228144704.12947-1-gregory.clement@bootlin.com\0" "ref\020180228144704.12947-3-gregory.clement@bootlin.com\0" "ref\020180228155350.0221a90f@windsurf.lan\0" - "From\0Gregory CLEMENT <gregory.clement@bootlin.com>\0" - "Subject\0Re: [PATCH 2/2] PCI: armada8k: Fix clock resource by adding a register clock\0" + "From\0gregory.clement@bootlin.com (Gregory CLEMENT)\0" + "Subject\0[PATCH 2/2] PCI: armada8k: Fix clock resource by adding a register clock\0" "Date\0Wed, 28 Feb 2018 16:37:24 +0100\0" - "To\0Thomas Petazzoni <thomas.petazzoni@bootlin.com>\0" - "Cc\0Andrew Lunn <andrew@lunn.ch>" - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> - Jason Cooper <jason@lakedaemon.net> - Antoine Tenart <antoine.tenart@bootlin.com> - linux-pci@vger.kernel.org - Hanna Hawa <hannah@marvell.com> - Omri Itach <omrii@marvell.com> - Nadav Haklai <nadavh@marvell.com> - Shadi Ammouri <shadi@marvell.com> - Igal Liberman <igall@marvell.com> - " Miqu\303\250l Raynal <miquel.raynal@bootlin.com>" - Bjorn Helgaas <bhelgaas@google.com> - Marcin Wojtas <mw@semihalf.com> - linux-arm-kernel@lists.infradead.org - " Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" - "SGkgVGhvbWFzLAogCiBPbiBtZXIuLCBmw6l2ci4gMjggMjAxOCwgVGhvbWFzIFBldGF6em9uaSA8\n" - "dGhvbWFzLnBldGF6em9uaUBib290bGluLmNvbT4gd3JvdGU6Cgo+IEhlbGxvLAo+Cj4gT24gV2Vk\n" - "LCAyOCBGZWIgMjAxOCAxNTo0NzowNCArMDEwMCwgR3JlZ29yeSBDTEVNRU5UIHdyb3RlOgo+PiBP\n" - "biBBcm1hZGEgN0svOEsgd2UgbmVlZCB0byBleHBsaWNpdGx5IGVuYWJsZSB0aGUgcmVnaXN0ZXIg\n" - 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This\n" + ">> clock is optional because not all the SoCs using this IP need it but at\n" + ">> least for Armada 7K/8K it is actually mandatory.\n" + ">> \n" + ">> The binding documentation is updated accordingly.\n" + ">> \n" + ">> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>\n" + ">> ---\n" + ">> Documentation/devicetree/bindings/pci/pci-armada8k.txt | 6 +++++-\n" + ">> drivers/pci/dwc/pcie-armada8k.c | 11 +++++++++++\n" + ">> 2 files changed, 16 insertions(+), 1 deletion(-)\n" + ">> \n" + ">> diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt\n" + ">> index c1e4c3d10a74..9948b1e9a8e5 100644\n" + ">> --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt\n" + ">> +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt\n" + ">> @@ -12,7 +12,11 @@ Required properties:\n" + ">> - \"ctrl\" for the control register region\n" + ">> - \"config\" for the config space region\n" + ">> - interrupts: Interrupt specifier for the PCIe controler\n" + ">> -- clocks: reference to the PCIe controller clock\n" + ">> +- clocks: reference to the PCIe controller clocks\n" + ">> +- clock-names: mandatory if there is a second clock, in this case the\n" + ">> + name must be \"core\" for the first clock and \"reg\" for the second\n" + ">> + one\n" + ">> +\n" + ">\n" + "> Unneeded new line added here.\n" + "will removed it\n" + "\n" + ">\n" + ">> \n" + ">> Example:\n" + ">> \n" + ">> diff --git a/drivers/pci/dwc/pcie-armada8k.c b/drivers/pci/dwc/pcie-armada8k.c\n" + ">> index f9b1aec25c5c..aa4e5cc4ab7b 100644\n" + ">> --- a/drivers/pci/dwc/pcie-armada8k.c\n" + ">> +++ b/drivers/pci/dwc/pcie-armada8k.c\n" + ">> @@ -28,6 +28,7 @@\n" + ">> struct armada8k_pcie {\n" + ">> \tstruct dw_pcie *pci;\n" + ">> \tstruct clk *clk;\n" + ">> +\tstruct clk *clk_reg;\n" + ">> };\n" + ">> \n" + ">> #define PCIE_VENDOR_REGS_OFFSET\t\t0x8000\n" + ">> @@ -229,6 +230,15 @@ static int armada8k_pcie_probe(struct platform_device *pdev)\n" + ">> \tif (ret)\n" + ">> \t\treturn ret;\n" + ">> \n" + ">> +\tif (IS_ERR(pcie->clk_reg) && PTR_ERR(pcie->clk_reg) == -EPROBE_DEFER) {\n" + ">> +\t\tclk_disable_unprepare(pcie->clk);\n" + ">> +\t\treturn -EPROBE_DEFER;\n" + ">> +\t}\n" + ">> +\tif (!IS_ERR(pcie->clk_reg)) {\n" + ">> +\t\tret = clk_prepare_enable(pcie->clk_reg);\n" + ">> +\t\tif (ret)\n" + ">> +\t\t\tgoto fail;\n" + ">> +\t}\n" + ">> \t/* Get the dw-pcie unit configuration/control registers base. */\n" + ">\n" + "> Missing new line between the end of the block and the next comment.\n" + ">\n" + "OK\n" + "\n" + "> Regarding the error handling, doesn't it make more sense to also use a\n" + "> goto label to disable pcie->clk when getting the second clock gets a\n" + "> -EPROBE_DEFER ?\n" + ">\n" + ">> \tbase = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"ctrl\");\n" + ">> \tpci->dbi_base = devm_pci_remap_cfg_resource(dev, base);\n" + ">> @@ -247,6 +257,7 @@ static int armada8k_pcie_probe(struct platform_device *pdev)\n" + ">> \treturn 0;\n" + ">> \n" + ">> fail:\n" + ">> +\tclk_disable_unprepare(pcie->clk_reg);\n" + ">\n" + "> So you are disabling/unpreparing the clock, which failed to\n" + "> prepare/enable ?\n" + "\n" + "I was thinking to a single user, in this case if the prepare/enable\n" + "failed then the disabling/unpreparing do nothing because the counter is\n" + "already to 0. But indeed in case of multiple users of the clock, then the\n" + "counter could be wrongly decrease. I will modify it by adding a other\n" + "label.\n" + "\n" + "Thanks,\n" + "\n" + "Gregory\n" + "\n" + ">\n" + ">> \tclk_disable_unprepare(pcie->clk);\n" + ">> \n" + ">> \treturn ret;\n" + ">\n" + "> Thomas\n" + "> -- \n" + "> Thomas Petazzoni, CTO, Bootlin (formerly Free Electrons)\n" + "> Embedded Linux and Kernel engineering\n" + "> http://bootlin.com\n" + "\n" + "-- \n" + "Gregory Clement, Bootlin (formerly Free Electrons)\n" + "Embedded Linux and Kernel engineering\n" + http://bootlin.com -aef0aeb3fd55da1eacd082b2a2d3a8bbeebe38d63e20e8691b8cebeb5c682208 +8276572fbfe10af50b96d2e29b50d4ffd862317c180980c5abfcb127e1bdb2e8
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