From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0AB27CD6E49 for ; Fri, 29 May 2026 20:45:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AAFAD112503; Fri, 29 May 2026 20:45:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="nTySKOWp"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 601E3112503 for ; Fri, 29 May 2026 20:45:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780087540; x=1811623540; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=pGgHTYyMsLDxQCOln/0vsxuRtEm1ETIn1xKrLSttrBI=; b=nTySKOWpL8Cj3f/yf9lCeXTa6h5AbtpGXS5raFc/yI61qTetMirQhH1H XplD9m04U2dygRa5EEnlqyFtCKf03YQ/RsElDkidq+xch+mBonAbjBP/P ojjgwpSK8bGuYiP8ycGfLeTeCYBhGhucIpdisSdIepHcZwWl45i76jbab UzlTRsTnOdhLp6nUtXYPmsQw7PjeHrLgN7LJKyEwJ/CY4oXboUpF4NV1y H0QyVwcd6A2nI+z2Gk+hxrq65yeZvm3yhOWV8Vjf/pE4flqejCHgToLN5 vo1dzthmM7ot4y8ijDpyXX3S65XOOi4tj8e3n1CqfL94e0DBDGnl8iMiU g==; X-CSE-ConnectionGUID: nciadbznTcqzXaMZrEntiw== X-CSE-MsgGUID: TS/5Q6N+QlSapZtNYLALMA== X-IronPort-AV: E=McAfee;i="6800,10657,11801"; a="81060013" X-IronPort-AV: E=Sophos;i="6.24,176,1774335600"; d="scan'208";a="81060013" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2026 13:45:40 -0700 X-CSE-ConnectionGUID: i4am2qi9S42xliQF558Tog== X-CSE-MsgGUID: C9J0vT2iS5yFeQD204jMjQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,176,1774335600"; d="scan'208";a="242816840" Received: from blai1-mobl2.amr.corp.intel.com (HELO adixit-MOBL3.intel.com) ([10.125.68.160]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2026 13:45:40 -0700 Date: Fri, 29 May 2026 13:45:39 -0700 Message-ID: <875x46lzbg.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa Cc: Subject: Re: [PATCH 5/9] drm/xe/rtp: Save OA nonpriv registers to register save/restore lists In-Reply-To: References: <20260518234716.1540123-1-ashutosh.dixit@intel.com> <20260518234716.1540123-6-ashutosh.dixit@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Wed, 27 May 2026 15:00:38 -0700, Umesh Nerlige Ramappa wrote: > > On Mon, May 18, 2026 at 04:47:12PM -0700, Ashutosh Dixit wrote: > > Now we can save OA whitelisting nonpriv registers to register save/restore > > lists. OA nonpriv registers are saved to both hwe->oa_sr as well as > > hwe->reg_sr, for reasons explained in coments. > > > > Signed-off-by: Ashutosh Dixit > > --- > > drivers/gpu/drm/xe/xe_reg_whitelist.c | 11 +++++++++++ > > 1 file changed, 11 insertions(+) > > > > diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c > > index 6d42c00c1d75b..18053582a6afa 100644 > > --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c > > +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c > > @@ -216,6 +216,17 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) > > > > xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist), > > &hwe->oa_whitelist, false); > > + /* > > + * Save oa nonpriv registers to hwe->oa_sr, from which oa registers are whitelisted > > + * or de-whitelisted, by toggling the 'deny' bit on oa stream open/close > > + */ > > + whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->oa_sr, nonpriv_slots); > > + > > + /* > > + * Also save oa nonpriv registers to hwe->reg_sr, to ensure oa registers are not > > + * whitelisted by default after probe/reset/restart > > + */ > > + whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, nonpriv_slots); > > I would prefer that we fail if the registers overshoot the max slots for > whitelisiting, but not sure why the overshoot is just a gt error log. Yes, this is pre-existing, but I believe it is to not fail the probe if we overshoot. The last time I ran into a situation like this, I was told that it is better to continue with reduced functionality, rather than no functionality at all. Also, xe_gt_err() will signal a failure in our CI, so the error will not be missed. > > Also, max NONPRIV slots should be bumped up to 20 for Xe. There is this: https://patchwork.freedesktop.org/patch/717191/?series=159772&rev=5 Though I believe the patch is incorrect, I will respond separately to this. A couple of other patches from the above series will also be nice to have. As I mentioned, I want to focus this series only on removing unconditional whitelisting for OA registers. Once this is merged, I am planning to have a follow-up series with changes such as this. E.g. the 'head' value in WHITELIST_OA_MERT_MMIO_TRG is incorrect (not a multiple of 16, as is required for RANGE_4), so that needs to be fixed too. Thanks. -- Ashutosh > > Umesh > > } > > > > /** > > -- > > 2.54.0 > >