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Wed, 07 Jan 2026 05:45:45 -0800 (PST) References: <20251216-upstream_pcie_rc-v7-0-4aeb0f53c4ce@aspeedtech.com> <875x9fuj7i.fsf@gmail.com> User-agent: mu4e 1.10.9; emacs 30.2 From: Mikhail Rudenko To: Jacky Chou Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Linus Walleij , Philipp Zabel , Neil Armstrong , "linux-aspeed@lists.ozlabs.org" , "linux-pci@vger.kernel.org" , "linux-phy@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Andrew Jeffery , "openbmc@lists.ozlabs.org" , "linux-gpio@vger.kernel.org" Subject: Re: [PATCH v7 0/7] Add ASPEED PCIe Root Complex support Date: Wed, 07 Jan 2026 16:40:09 +0300 In-reply-to: Message-ID: <875x9dcz9c.fsf@gmail.com> X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Type: text/plain Hi Jacky, On 2026-01-07 at 02:28 GMT, Jacky Chou wrote: > Hi Mikhail Rudenko, > >> First of all, thank you for your efforts in getting this driver upstreamed! I am >> trying to understand whether this driver supports PCIe devices that have an I/O >> port BAR, where CPU access to I/O ports is required for proper device >> operation. >> >> If I understand correctly, this line in the Aspeed 2600 dtsi file declares the I/O >> port range: >> >> ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000 >> >> During system initialization, the pci_remap_iospace() function in >> arch/arm/mm/ioremap.c maps the physical address range >> 0x00018000-0x00020000 to the virtual address PCI_IO_VIRT_BASE >> (0xfee00000). After this mapping, inb() and outb() calls work by converting I/O >> port addresses to virtual addresses starting at PCI_IO_VIRT_BASE, then >> performing reads and writes to those virtual addresses. >> >> What I don't understand is this: according to the Aspeed 2600 datasheet, the >> address range 0x00000000-0x0fffffff (which contains >> 0x00018000-0x00020000) is mapped to Firmware SPI Memory. This would >> mean that outb() operations get routed to memory-mapped SPI flash instead of >> PCIe. >> >> It seems like there's a missing piece to this puzzle. Could you help clarify how >> this is supposed to work? >> > > Thank you for pointing this out, and sorry for the confusion. > > You are correct that, as things stand, this does not make sense from a real hardware perspective. > > In fact, the I/O addressing support you noticed was something we experimented with internally > only. There is no actual hardware design on AST2600 that supports PCIe I/O port addressing in > this way. To enable those experiments, we modified our internal kernel accordingly, but this was > never intended to represent real, supported hardware behavior. > > This is our mistake for leaving this description in the DTS, as it can indeed be misleading. We > will remove this part to avoid further confusion. > > Thank you again for your careful review and for bringing this to our attention. Thank you for prompt reply and for getting this clarified! > Thanks, > Jacky -- Kind regards, Mikhail From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D5B22CFD62D for ; Wed, 7 Jan 2026 13:45:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:In-reply-to: Date:Subject:Cc:To:From:References:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=JG5pRkCjhHAD+YMAAwKZE5hM+WxW6ajReAeP8YOCL0U=; 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Wed, 07 Jan 2026 05:45:45 -0800 (PST) References: <20251216-upstream_pcie_rc-v7-0-4aeb0f53c4ce@aspeedtech.com> <875x9fuj7i.fsf@gmail.com> User-agent: mu4e 1.10.9; emacs 30.2 From: Mikhail Rudenko To: Jacky Chou Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Linus Walleij , Philipp Zabel , Neil Armstrong , "linux-aspeed@lists.ozlabs.org" , "linux-pci@vger.kernel.org" , "linux-phy@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Andrew Jeffery , "openbmc@lists.ozlabs.org" , "linux-gpio@vger.kernel.org" Subject: Re: [PATCH v7 0/7] Add ASPEED PCIe Root Complex support Date: Wed, 07 Jan 2026 16:40:09 +0300 In-reply-to: Message-ID: <875x9dcz9c.fsf@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260107_054548_709181_396A31F9 X-CRM114-Status: GOOD ( 18.88 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Hi Jacky, On 2026-01-07 at 02:28 GMT, Jacky Chou wrote: > Hi Mikhail Rudenko, > >> First of all, thank you for your efforts in getting this driver upstreamed! I am >> trying to understand whether this driver supports PCIe devices that have an I/O >> port BAR, where CPU access to I/O ports is required for proper device >> operation. >> >> If I understand correctly, this line in the Aspeed 2600 dtsi file declares the I/O >> port range: >> >> ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000 >> >> During system initialization, the pci_remap_iospace() function in >> arch/arm/mm/ioremap.c maps the physical address range >> 0x00018000-0x00020000 to the virtual address PCI_IO_VIRT_BASE >> (0xfee00000). After this mapping, inb() and outb() calls work by converting I/O >> port addresses to virtual addresses starting at PCI_IO_VIRT_BASE, then >> performing reads and writes to those virtual addresses. >> >> What I don't understand is this: according to the Aspeed 2600 datasheet, the >> address range 0x00000000-0x0fffffff (which contains >> 0x00018000-0x00020000) is mapped to Firmware SPI Memory. This would >> mean that outb() operations get routed to memory-mapped SPI flash instead of >> PCIe. >> >> It seems like there's a missing piece to this puzzle. Could you help clarify how >> this is supposed to work? >> > > Thank you for pointing this out, and sorry for the confusion. > > You are correct that, as things stand, this does not make sense from a real hardware perspective. > > In fact, the I/O addressing support you noticed was something we experimented with internally > only. There is no actual hardware design on AST2600 that supports PCIe I/O port addressing in > this way. To enable those experiments, we modified our internal kernel accordingly, but this was > never intended to represent real, supported hardware behavior. > > This is our mistake for leaving this description in the DTS, as it can indeed be misleading. We > will remove this part to avoid further confusion. > > Thank you again for your careful review and for bringing this to our attention. Thank you for prompt reply and for getting this clarified! > Thanks, > Jacky -- Kind regards, Mikhail -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy