From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6C793C4167B for ; Tue, 5 Dec 2023 16:30:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 36E7B10E043; Tue, 5 Dec 2023 16:30:40 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 10BE510E043 for ; Tue, 5 Dec 2023 16:30:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701793838; x=1733329838; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=leof3sLokk4dN5gHODhODVp95xk4M8zf7DA/qjy4cNw=; b=NuV5HNyBtYU9B6e9iE8CDdty/P4wMEVGT7WsNjW4+Rn128pooHx8CEQj SErGpqQUYNTKVCWfGJRlL7auh+XJ+7VcpKaKMiwyGpBWUL+8yP+4WOTHY bpfz4x+k5iTCgTAkSr3+KHhwRPjCmJIn3LTzrL4/pvk32Z7RwQE+gsMFl jvkIpaz77DmKKMc8NxXLIW4TfkCXp1+62s/dB02mqx1Uuhtt63IOuK8qU HOmLTymFHV5V7APt3eP/KuylpxG3u9L3YnhGbrxp5srg9XFpYypV58R3d hbW/LFFetOM+XEBzAdFNMccWBZtb+YtThvMujREHKiVClKxqFyhV8hjg6 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="384323372" X-IronPort-AV: E=Sophos;i="6.04,252,1695711600"; d="scan'208";a="384323372" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2023 08:30:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="841519164" X-IronPort-AV: E=Sophos;i="6.04,252,1695711600"; d="scan'208";a="841519164" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.209.68.234]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2023 08:30:37 -0800 Date: Tue, 05 Dec 2023 08:24:37 -0800 Message-ID: <875y1c4ny2.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Lucas De Marchi In-Reply-To: <20231205155820.2133813-1-lucas.demarchi@intel.com> References: <20231205155820.2133813-1-lucas.demarchi@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-xe] [PATCH] drm/xe: Expand XE_REG_OPTION_MASKED documentation X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matt Roper , intel-xe@lists.freedesktop.org Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Tue, 05 Dec 2023 07:58:20 -0800, Lucas De Marchi wrote: > > Expand documentation and add an example to make clear this isn't about > generic masks in registers. Also, fix the doc regarding read operations: > the mask part has no effect on them. Reviewed-by: Ashutosh Dixit > Signed-off-by: Lucas De Marchi > --- > drivers/gpu/drm/xe/regs/xe_reg_defs.h | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/xe/regs/xe_reg_defs.h b/drivers/gpu/drm/xe/regs/xe_reg_defs.h > index 6e20fc2de9ff..c50e7650c09a 100644 > --- a/drivers/gpu/drm/xe/regs/xe_reg_defs.h > +++ b/drivers/gpu/drm/xe/regs/xe_reg_defs.h > @@ -60,7 +60,16 @@ struct xe_reg_mcr { > > /** > * XE_REG_OPTION_MASKED - Register is "masked", with upper 16 bits marking the > - * read/written bits on the lower 16 bits. > + * written bits on the lower 16 bits. > + * > + * It only applies to registers explicitly marked in bspec with > + * "Access: Masked". Registers with this option can have write operations to > + * specific lower bits by setting the corresponding upper bits. Other bits will > + * not be affected. This allows register writes without needing a RMW cycle and > + * without caching in software the register value. > + * > + * Example: a write with value 0x00010001 will set bit 0 and all other bits > + * retain their previous values. > * > * To be used with XE_REG(). XE_REG_MCR() and XE_REG_INITIALIZER() > */ > -- > 2.40.1 >