From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18296C0032E for ; Fri, 20 Oct 2023 19:45:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:References :In-Reply-To:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=g+BYXRTZaiyi86DiX5+XuLNcANeAGqTBaloWX6FZW9Y=; b=Ouv4vomJ3RhDUU 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Message-ID: <875y31cc2y.fsf@all.your.base.are.belong.to.us> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231020_124530_838699_D1BAFEFA X-CRM114-Status: GOOD ( 50.17 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Conor Dooley , Saravana Kannan , Marc Zyngier , Anup Patel , Atish Patra , linux-kernel@vger.kernel.org, Rob Herring , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , Thomas Gleixner , Frank Rowand , linux-riscv@lists.infradead.org, Andrew Jones Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org QW51cCBQYXRlbCA8YXBhdGVsQHZlbnRhbmFtaWNyby5jb20+IHdyaXRlczoKCj4gT24gRnJpLCBP Y3QgMjAsIDIwMjMgYXQgMTA6MDfigK9QTSBCasO2cm4gVMO2cGVsIDxiam9ybkBrZXJuZWwub3Jn PiB3cm90ZToKPj4KPj4gQW51cCBQYXRlbCA8YXBhdGVsQHZlbnRhbmFtaWNyby5jb20+IHdyaXRl czoKPj4KPj4gPiBPbiBGcmksIE9jdCAyMCwgMjAyMyBhdCA4OjEw4oCvUE0gQmrDtnJuIFTDtnBl bCA8Ympvcm5Aa2VybmVsLm9yZz4gd3JvdGU6Cj4+ID4+Cj4+ID4+IEFudXAgUGF0ZWwgPGFwYXRl bEB2ZW50YW5hbWljcm8uY29tPiB3cml0ZXM6Cj4+ID4+Cj4+ID4+ID4gT24gRnJpLCBPY3QgMjAs IDIwMjMgYXQgMjoxN+KAr1BNIEJqw7ZybiBUw7ZwZWwgPGJqb3JuQGtlcm5lbC5vcmc+IHdyb3Rl Ogo+PiA+PiA+Pgo+PiA+PiA+PiBUaGFua3MgZm9yIHRoZSBxdWljayByZXBseSEKPj4gPj4gPj4K Pj4gPj4gPj4gQW51cCBQYXRlbCA8YXBhdGVsQHZlbnRhbmFtaWNyby5jb20+IHdyaXRlczoKPj4g Pj4gPj4KPj4gPj4gPj4gPiBPbiBUaHUsIE9jdCAxOSwgMjAyMyBhdCA3OjEz4oCvUE0gQmrDtnJu IFTDtnBlbCA8Ympvcm5Aa2VybmVsLm9yZz4gd3JvdGU6Cj4+ID4+ID4+ID4+Cj4+ID4+ID4+ID4+ IEhpIEFudXAsCj4+ID4+ID4+ID4+Cj4+ID4+ID4+ID4+IEFudXAgUGF0ZWwgPGFwYXRlbEB2ZW50 YW5hbWljcm8uY29tPiB3cml0ZXM6Cj4+ID4+ID4+ID4+Cj4+ID4+ID4+ID4+ID4gVGhlIFJJU0Mt ViBBSUEgc3BlY2lmaWNhdGlvbiBpcyByYXRpZmllZCBhcy1wZXIgdGhlIFJJU0MtViBpbnRlcm5h dGlvbmFsCj4+ID4+ID4+ID4+ID4gcHJvY2Vzcy4gVGhlIGxhdGVzdCByYXRpZmllZCBBSUEgc3Bl Y2lmY2F0aW9uIGNhbiBiZSBmb3VuZCBhdDoKPj4gPj4gPj4gPj4gPiBodHRwczovL2dpdGh1Yi5j b20vcmlzY3YvcmlzY3YtYWlhL3JlbGVhc2VzL2Rvd25sb2FkLzEuMC9yaXNjdi1pbnRlcnJ1cHRz LTEuMC5wZGYKPj4gPj4gPj4gPj4gPgo+PiA+PiA+PiA+PiA+IEF0IGEgaGlnaC1sZXZlbCwgdGhl IEFJQSBzcGVjaWZpY2F0aW9uIGFkZHMgdGhyZWUgdGhpbmdzOgo+PiA+PiA+PiA+PiA+IDEpIEFJ QSBDU1JzCj4+ID4+ID4+ID4+ID4gICAgLSBJbXByb3ZlZCBsb2NhbCBpbnRlcnJ1cHQgc3VwcG9y dAo+PiA+PiA+PiA+PiA+IDIpIEluY29taW5nIE1lc3NhZ2UgU2lnbmFsZWQgSW50ZXJydXB0IENv bnRyb2xsZXIgKElNU0lDKQo+PiA+PiA+PiA+PiA+ICAgIC0gUGVyLUhBUlQgTVNJIGNvbnRyb2xs ZXIKPj4gPj4gPj4gPj4gPiAgICAtIFN1cHBvcnQgTVNJIHZpcnR1YWxpemF0aW9uCj4+ID4+ID4+ ID4+ID4gICAgLSBTdXBwb3J0IElQSSBhbG9uZyB3aXRoIHZpcnR1YWxpemF0aW9uCj4+ID4+ID4+ ID4+ID4gMykgQWR2YW5jZWQgUGxhdGZvcm0tTGV2ZWwgSW50ZXJydXB0IENvbnRyb2xsZXIgKEFQ TElDKQo+PiA+PiA+PiA+PiA+ICAgIC0gV2lyZWQgaW50ZXJydXB0IGNvbnRyb2xsZXIKPj4gPj4g Pj4gPj4gPiAgICAtIEluIE1TSS1tb2RlLCBjb252ZXJ0cyB3aXJlZCBpbnRlcnJ1cHQgaW50byBN U0lzIChpLmUuIE1TSSBnZW5lcmF0b3IpCj4+ID4+ID4+ID4+ID4gICAgLSBJbiBEaXJlY3QtbW9k ZSwgaW5qZWN0cyBleHRlcm5hbCBpbnRlcnJ1cHRzIGRpcmVjdGx5IGludG8gSEFSVHMKPj4gPj4g Pj4gPj4KPj4gPj4gPj4gPj4gVGhhbmtzIGZvciB3b3JraW5nIG9uIHRoZSBBSUEgc3VwcG9ydCEg SSBoYWQgYSBsb29rIGF0IHRoZSBzZXJpZXMsIGFuZAo+PiA+PiA+PiA+PiBoYXZlIHNvbWUgY29u Y2VybnMgYWJvdXQgaW50ZXJydXB0IElEIGFic3RyYWN0aW9uLgo+PiA+PiA+PiA+Pgo+PiA+PiA+ PiA+PiBBIGJpdCBvZiBiYWNrZ3JvdW5kLCBmb3IgcmVhZGVycyBub3QgZmFtaWxpYXIgd2l0aCB0 aGUgQUlBIGRldGFpbHMuCj4+ID4+ID4+ID4+Cj4+ID4+ID4+ID4+IElNU0lDIGFsbG93cyBmb3Ig MjA0NyB1bmlxdWUgTVNJICgibXNpLWlycSIpIHNvdXJjZXMgcGVyIGhhcnQsIGFuZAo+PiA+PiA+ PiA+PiBlYWNoIE1TSSBpcyBkZWRpY2F0ZWQgdG8gYSBjZXJ0YWluIGhhcnQuIFRoZSBzZXJpZXMg dGFrZXMgdGhlIGFwcHJvYWNoCj4+ID4+ID4+ID4+IHRvIHNheSB0aGF0IHRoZXJlIGFyZSwgZS5n LiwgMjA0NyBpbnRlcnJ1cHRzICgibG54LWlycSIpIGdsb2JhbGx5Lgo+PiA+PiA+PiA+PiBFYWNo IGxueC1pcnEgY29uc2lzdHMgb2YgI2hhcnRzICogbXNpLWlycSAtLSBhIHNsaWNlIC0tIGFuZCBp biB0aGUKPj4gPj4gPj4gPj4gc2xpY2Ugb25seSAqb25lKiBtc2ktaXJxIGlzIGFjdXRhbGx5IHVz ZWQuCj4+ID4+ID4+ID4+Cj4+ID4+ID4+ID4+IFRoaXMgc2NoZW1lIG1ha2VzIGFmZmluaXR5IGNo YW5nZXMgbW9yZSByb2J1c3QsIGJlY2F1c2UgdGhlIGludGVycnVwdAo+PiA+PiA+PiA+PiBzb3Vy Y2VzIG9uICJvdGhlciIgaGFydHMgYXJlIHByZS1hbGxvY2F0ZWQuIE9uIHRoZSBvdGhlciBoYW5k IGl0Cj4+ID4+ID4+ID4+IHJlcXVpcmVzIHRvIHByb3BhZ2F0ZSBpcnEgbWFza2luZyB0byBvdGhl ciBoYXJ0cyB2aWEgSVBJcyAodGhpcyBpcwo+PiA+PiA+PiA+PiBtb3N0bHkgZG9uZSB1cCBzZXR1 cC90ZWFyIGRvd24pLiBJdCdzIGFsc28gd2FzdGVmdWwsIGJlY2F1c2UgbXNpLWlycXMKPj4gPj4g Pj4gPj4gYXJlIGhvZ2dlZCwgYW5kIGNhbm5vdCBiZSB1c2VkLgo+PiA+PiA+PiA+Pgo+PiA+PiA+ PiA+PiBDb250ZW1wb3Jhcnkgc3RvcmFnZS9uZXR3b3JraW5nIGRyaXZlcnMgdXN1YWxseSB1c2Vz IHF1ZXVlcyBwZXIgY29yZQo+PiA+PiA+PiA+PiAob3IgYSBzdWItc2V0IG9mIGNvcmVzKS4gVGhl IGN1cnJlbnQgc2NoZW1lIHdhc3RlcyBhIGxvdCBvZiBtc2ktaXJxcy4KPj4gPj4gPj4gPj4gSWYg d2UgaW5zdGVhZCB1c2VkIGEgc2NoZW1lIHdoZXJlICJtc2ktaXJxID09IGxueC1pcnEiLCBpbnN0 ZWFkIG9mCj4+ID4+ID4+ID4+ICJsbnEtaXJxID0ge2hhcnQgMDttc2ktaXJxIHggLCAuLi4gaGFy dCBOO21zaS1pcnEgeH0iLCB0aGVyZSB3b3VsZCBiZQo+PiA+PiA+PiA+PiBhIGxvdCBNU0lzIGZv ciBvdGhlciB1c2Vycy4gMS0xIHZzIDEtTi4gRS5nLiwgaWYgYSBzdG9yYWdlIGRldmljZQo+PiA+ PiA+PiA+PiB3b3VsZCBsaWtlIHRvIHVzZSA1IHF1ZXVlcyAoNSBjb3Jlcykgb24gYSAxMjggY29y ZSBzeXN0ZW0sIHRoZSBjdXJyZW50Cj4+ID4+ID4+ID4+IHNjaGVtZSB3b3VsZCBjb25zdW1lIDUg KiAxMjggTVNJcywgaW5zdGVhZCBvZiBqdXN0IDUuCj4+ID4+ID4+ID4+Cj4+ID4+ID4+ID4+IE9u IHRoZSBwbHVzIHNpZGU6Cj4+ID4+ID4+ID4+ICogQ2hhbmdpbmcgaW50ZXJydXB0cyBhZmZpbml0 eSB3aWxsIG5ldmVyIGZhaWwsIGJlY2F1c2UgdGhlIGludGVycnVwdHMKPj4gPj4gPj4gPj4gICBv biBlYWNoIGhhcnQgaXMgcHJlLWFsbG9jYXRlZC4KPj4gPj4gPj4gPj4KPj4gPj4gPj4gPj4gT24g dGhlIG5lZ2F0aXZlIHNpZGU6Cj4+ID4+ID4+ID4+ICogV2FzdGVmdWwgaW50ZXJydXB0IHVzYWdl LCBhbmQgYSBzeXN0ZW0gY2FuIHBvdGllbnRpYWxseSAicnVuIG91dCIgb2YKPj4gPj4gPj4gPj4g ICBpbnRlcnJ1cHRzLiBFc3BlY2lhbGx5IGZvciBtYW55IGNvcmUgc3lzdGVtcy4KPj4gPj4gPj4g Pj4gKiBJbnRlcnJ1cHQgbWFza2luZyBuZWVkIHRvIHByb2FnYXRlIHRvIGhhcnRzIHZpYSBJUElz ICh0aGVyZSdzIG5vCj4+ID4+ID4+ID4+ICAgYnJvYWRjYXN0IGNzciBpbiBJTVNJQyksIGFuZCBh IG1vcmUgY29tcGxleCBsb2NraW5nIHNjaGVtZSBJTVNJQwo+PiA+PiA+PiA+Pgo+PiA+PiA+PiA+ PiBTdW1tYXJ5Ogo+PiA+PiA+PiA+PiBUaGUgY3VycmVudCBzZXJpZXMgY2FwcyB0aGUgbnVtYmVy IG9mIGdsb2JhbCBpbnRlcnJ1cHRzIHRvIG1heGltdW0KPj4gPj4gPj4gPj4gMjA0NyBNU0lzIGZv ciBhbGwgY29yZXMgKHdob2xlIHN5c3RlbSkuIEEgYmV0dGVyIHNjaGVtZSwgSU1PLCB3b3VsZCBi ZQo+PiA+PiA+PiA+PiB0byBleHBvc2UgMjA0NyAqICNoYXJ0cyB1bmlxdWUgTVNJcy4KPj4gPj4g Pj4gPj4KPj4gPj4gPj4gPj4gSSB0aGluayB0aGlzIGNvdWxkIHNpbXBsaWZ5L3JlbW92ZSg/KSB0 aGUgbG9ja2luZyBhcyB3ZWxsLgo+PiA+PiA+PiA+Cj4+ID4+ID4+ID4gRXhwb3NpbmcgMjA0NyAq ICNoYXJ0cyB1bmlxdWUgTVNJcyBoYXMgbXVsdGlwbGUgaXNzdWVzOgo+PiA+PiA+PiA+IDEpIFRo ZSBpcnFfc2V0X2FmZmluaXR5KCkgZG9lcyBub3Qgd29yayBmb3IgTVNJcyBiZWNhdXNlIGVhY2gK Pj4gPj4gPj4gPiAgICAgIElSUSBpcyBub3QgdGllZCB0byBhIHBhcnRpY3VsYXIgSEFSVC4gVGhp cyBtZWFucyB3ZSBjYW4ndAo+PiA+PiA+PiA+ICAgICAgYmFsYW5jZSB0aGUgSVJRIHByb2Nlc3Np bmcgbG9hZCBhbW9uZyBIQVJUcy4KPj4gPj4gPj4KPj4gPj4gPj4gWWVzLCB5b3UgY2FuIGJhbGFu Y2UuIEluIHlvdXIgY29kZSwgZWFjaCAqYWN0aXZlKiBNU0kgaXMgc3RpbGwKPj4gPj4gPj4gYm91 bmQvYWN0aXZlIHRvIGEgc3BlY2lmaWMgaGFyZCB0b2dldGhlciB3aXRoIHRoZSBhZmZpbml0eSBt YXNrLiBJbiBhbgo+PiA+PiA+PiAxLTEgbW9kZWwgeW91IHdvdWxkIHN0aWxsIG5lZWQgdG8gdHJh Y2sgdGhlIGFmZmluaXR5IG1hc2ssIGJ1dCB0aGUKPj4gPj4gPj4gaXJxX3NldF9hZmZpbml0eSgp IHdvdWxkIGJlIGRpZmZlcmVudC4gSXQgd291bGQgdHJ5IHRvIGFsbG9jYXRlIGEgbmV3Cj4+ID4+ ID4+IE1TSSBmcm9tIHRoZSB0YXJnZXQgQ1BVLCBhbmQgdGhlbiBzd2l0Y2ggdG8gaGF2aW5nIHRo YXQgTVNJIGFjdGl2ZS4KPj4gPj4gPj4KPj4gPj4gPj4gVGhhdCdzIHdoYXQgeDg2IGRvZXMgQUZB SVUsIHdoaWNoIGlzIGFsc28gY29uc3RyYWluZWQgYnkgdGhlICMgb2YKPj4gPj4gPj4gYXZhaWxh YmxlIE1TSXMuCj4+ID4+ID4+Cj4+ID4+ID4+IFRoZSBkb3duc2lkZSwgYXMgSSBwb2ludGVkIG91 dCwgaXMgdGhhdCB0aGUgc2V0IGFmZmluaXR5IGFjdGlvbiBjYW4KPj4gPj4gPj4gZmFpbCBmb3Ig YSBjZXJ0YWluIHRhcmdldCBDUFUuCj4+ID4+ID4KPj4gPj4gPiBZZXMsIGlycV9zZXRfYWZmaW5p dHkoKSBjYW4gZmFpbCBmb3IgdGhlIHN1Z2dlc3RlZCBhcHByb2FjaCBwbHVzIGZvcgo+PiA+PiA+ IFJJU0MtViBBSUEsIG9uZSBIQVJUIGRvZXMgbm90IGhhdmUgYWNjZXNzIHRvIG90aGVyIEhBUlRz Cj4+ID4+ID4gTVNJIGVuYWJsZS9kaXNhYmxlIGJpdHMgc28gdGhlIGFwcHJvYWNoIHdpbGwgYWxz byBpbnZvbHZlIElQSS4KPj4gPj4KPj4gPj4gQ29ycmVjdCwgYnV0IHRoZSBjdXJyZW50IHNlcmll cyBkb2VzIGEgYnJvYWRjYXN0IHRvIGFsbCBjb3Jlcywgd2hlcmUgdGhlCj4+ID4+IDEtMSBhcHBy b2FjaCBpcyBhdCBtb3N0IGFuIElQSSB0byBhIHNpbmdsZSBjb3JlLgo+PiA+Pgo+PiA+PiAxMjgr YyBtYWNoaW5lcyBhcmUgZ2V0dGluZyBtb3JlIGNvbW1vbiwgYW5kIHlvdSBoYXZlIGRldmljZXMg dGhhdCB5b3UKPj4gPj4gYnJpbmcgdXAvZG93biBvbiBhIHBlci1jb3JlIGJhc2lzLiBCcm9hZGNh c3RpbmcgSVBJcyB0byBhbGwgY29yZXMsIHdoZW4KPj4gPj4gZGVhbGluZyB3aXRoIGEgcGVyLWNv cmUgYWN0aXZpdHkgaXMgYSBwcmV0dHkgbm9pc3kgbmVpZ2hib3IuCj4+ID4KPj4gPiBCcm9hZGNh c3QgSVBJIGluIHRoZSBjdXJyZW50IGFwcHJvYWNoIGlzIG9ubHkgZG9uZSB1cG9uIE1TSSBtYXNr L3VubWFzawo+PiA+IG9wZXJhdGlvbi4gSXQgaXMgbm90IGRvbmUgdXBvbiBzZXRfYWZmaW5pdHko KSBvZiBpbnRlcnJ1cHQgaGFuZGxpbmcuCj4+Cj4+IEknbSBhd2FyZS4gV2UncmUgb24gdGhlIHNh bWUgcGFnZSBoZXJlLgo+Pgo+PiA+Pgo+PiA+PiBUaGlzIGNvdWxkIGJlIGZpeGVkIGluIHRoZSBl eGlzdGluZyAxLW4gYXBwcm9hY2gsIGJ5IG5vdCByZXF1aXJlIHRvIHN5bmMKPj4gPj4gdGhlIGNv cmVzIHRoYXQgYXJlIG5vdCBoYW5kbGluZyB0aGUgTVNJIGluIHF1ZXN0aW9uLiAiTGF6eSBkaXNh YmxlIgo+PiA+Cj4+ID4gSW5jb3JyZWN0LiBUaGUgYXBwcm9hY2ggeW91IGFyZSBzdWdnZXN0aW5n IGludm9sdmVzIGFuIElQSSB1cG9uIGV2ZXJ5Cj4+ID4gaXJxX3NldF9hZmZpbml0eSgpLiBUaGlz IGlzIGJlY2F1c2UgYSBIQVJUIGNhbiBvbmx5IGVuYWJsZSBpdCdzIG93bgo+PiA+IE1TSSBJRCBz byB3aGVuIGFuIElSUSBpcyBtb3ZlZCB0byBmcm9tIEhBUlQgQSB0byBIQVJUIEIgd2l0aAo+PiA+ IGEgZGlmZmVyZW50IElEIFggb24gSEFSVCBCIHRoZW4gd2Ugd2lsbCBuZWVkIGFuIElQSSBpbiBp cnFfc2V0X2FmZmluaXQoKQo+PiA+IHRvIGVuYWJsZSBJRCBYIG9uIEhBUlQgQi4KPj4KPj4gWWVz LCB0aGUgMS0xIGFwcHJvYWNoIHdpbGwgcmVxdWlyZSBhbiBJUEkgdG8gb25lIHRhcmdldCBjcHUg b24gYWZmaW5pdHkKPj4gY2hhbmdlcywgYW5kIHNpbWlsYXIgb24gbWFzay91bm1hc2suCj4+Cj4+ IFRoZSAxLW4gYXBwcm9hY2gsIHJlcXVpcmUgbm8tSVBJIG9uIGFmZmluaXR5IGNoYW5nZXMgKG5p Y2UhKSwgYnV0IElQSQo+PiBicm9hZGNhc3QgdG8gYWxsIGNvcmVzIG9uIG1hc2svdW5tYXNrIChu b3Qgc28gbmljZSkuCj4+Cj4+ID4+ID4+IE15IGNvbmNlcm4gaXMgaW50ZXJydXB0cyBiZWNvbWUg YSBzY2FyY2UgcmVzb3VyY2Ugd2l0aCB0aGlzCj4+ID4+ID4+IGltcGxlbWVudGF0aW9uLCBidXQg bWF5YmUgbXkgdmlldyBpcyBpbmNvcnJlY3QuIEkndmUgc2VlbiBiYXJlLW1ldGFsCj4+ID4+ID4+ IHg4NiBzeXN0ZW1zIChubyBWTXMpIHdpdGggfjIwMCBjb3JlcywgYW5kIH4yMDAwIGludGVycnVw dHMsIGJ1dCBtYXliZQo+PiA+PiA+PiB0aGF0IGlzIGNvbnNpZGVyZWQgImEgbG90IG9mIGludGVy cnVwdHMiLgo+PiA+PiA+Pgo+PiA+PiA+PiBBcyBsb25nIGFzIHdlIGRvbid0IGdldCBpbnRvIHNj ZW5hcmlvcyB3aGVyZSB3ZSdyZSBydW5uaW5nIG91dCBvZgo+PiA+PiA+PiBpbnRlcnJ1cHRzLCBk dWUgdG8gdGhlIHNvZnR3YXJlIGRlc2lnbi4KPj4gPj4gPj4KPj4gPj4gPgo+PiA+PiA+IFRoZSBj dXJyZW50IGFwcHJvYWNoIGlzIHNpbXBsZXIgYW5kIGVuc3VyZXMgaXJxX3NldF9hZmZpbml0eQo+ PiA+PiA+IGFsd2F5cyB3b3Jrcy4gVGhlIGxpbWl0IG9mIG1heCAyMDQ3IElEcyBpcyBzdWZmaWNp ZW50IGZvciBtYW55Cj4+ID4+ID4gc3lzdGVtcyAoaWYgbm90IGFsbCkuCj4+ID4+Cj4+ID4+IExl dCBtZSBnaXZlIHlvdSBhbm90aGVyIHZpZXcuIE9uIGEgMTI4YyBzeXN0ZW0gZWFjaCBjb3JlIGhh cyB+MTYgdW5pcXVlCj4+ID4+IGludGVycnVwdHMgZm9yIGRpc3Bvc2FsLiBFLmcuIHRoZSBJbnRl bCBFODAwIE5JQyBoYXMgbW9yZSB0aGFuIDIwNDgKPj4gPj4gbmV0d29yayBxdWV1ZSBwYWlycyBm b3IgZWFjaCBQRi4KPj4gPgo+PiA+IENsZWFybHksIHRoaXMgZXhhbXBsZSBpcyBhIGh5cG90aGV0 aWNhbCBhbmQgcmVwcmVzZW50cyBhIHBvb3JseQo+PiA+IGRlc2lnbmVkIHBsYXRmb3JtLgo+PiA+ Cj4+ID4gSGF2aW5nIGp1c3QgMTYgSURzIHBlci1Db3JlIGlzIGEgdmVyeSBwb29yIGRlc2lnbiBj aG9pY2UuIEluIGZhY3QsIHRoZQo+PiA+IFNlcnZlciBTb0Mgc3BlYyBtYW5kYXRlcyBhIG1pbmlt dW0gMjU1IElEcy4KPj4KPj4gWW91IGFyZSBtaXNyZWFkaW5nLiBBIDEyOGMgc3lzdGVtIHdpdGgg MjA0NyBNU0lzIHBlci1jb3JlLCB3aWxsIG9ubHkKPj4gaGF2ZSAxNiAqcGVyLWNvcmUgdW5pcXVl KiAoMjA0Ny8xMjgpIGludGVycnVwdHMgd2l0aCB0aGUgY3VycmVudCBzZXJpZXMuCj4+Cj4+IEkn bSBub3Qgc2F5aW5nIHRoYXQgZWFjaCBJTVNJQyBoYXMgMTYgSURzLCBJJ20gc2F5aW5nIHRoYXQg aW4gYSAxMjhjCj4+IHN5c3RlbSB3aXRoIHRoZSBtYXhpbXVtIGFtb3VudCBvZiBNU0lzIHBvc3Np YmxlIGluIHRoZSBzcGVjLCB5b3UnbGwgZW5kCj4+IHVwIHdpdGggMTYgKnVuaXF1ZSogaW50ZXJy dXB0cyBwZXIgY29yZS4KPgo+IC1FTk9QQVJTRQo+Cj4gSSBkb24ndCBzZWUgaG93IHRoaXMgYXBw bGllcyB0byB0aGUgY3VycmVudCBhcHByb2FjaCBiZWNhdXNlIHdlIHRyZWF0Cj4gTVNJIElEIHNw YWNlIGFzIGdsb2JhbCBhY3Jvc3MgY29yZXMgc28gaWYgYSBzeXN0ZW0gaGFzIDIwNDcgTVNJcwo+ IHBlci1jb3JlIHRoZW4gd2UgaGF2ZSAyMDQ3IE1TSXMgYWNyb3NzIGFsbCBjb3Jlcy4KCk9rLCBJ J2xsIHRyeSBhZ2FpbiEgOi0pCgpMZXQncyBhc3N1bWUgdGhhdCBlYWNoIGNvcmUgaW4gdGhlIDEy OGMgc3lzdGVtIGhhcyBzb21lIHBlci1jb3JlCnJlc291cmNlcywgc2F5IGEgdHdvIE5JQyBxdWV1 ZSBwYWlycywgYW5kIGEgc3RvcmFnZSBxdWV1ZSBwYWlyLiBUaGlzCndpbGwgY29uc3VtZSwgZS5n LiwgMioyICsgMiAoNikgTVNJIHNvdXJjZXMgZnJvbSB0aGUgZ2xvYmFsIG5hbWVzcGFjZS4KCklm IGVhY2ggY29yZSBkb2VzIHRoaXMgaXQnbGwgYmUgNioxMjggTVNJIHNvdXJjZXMgb2YgdGhlIGds b2JhbApuYW1lc3BhY2UuCgpUaGUgbWF4aW11bSBudW1iZXIgb2YgInByaXZhdGVzIiBNU0kgc291 cmNlcyBhIGNvcmUgY2FuIHV0aWxpemUgaXMgMTYuCgpJJ20gdHJ5aW5nIChpdCdzIGRvZXMgc2Vl bSB0byBnbyB0aGF0IHdlbGwgOy0pKSB0byBwb2ludCBvdXQgdGhhdCBpdCdzCm9ubHkgMTYgdW5p cXVlIHNvdXJjZXMgcGVyIGNvcmUuIEZvciwgc2F5LCBhIDI1NiBjb3JlIHN5c3RlbSBpdCB3b3Vs ZCBiZQo4LiAyMDQ3IE1TSSBzb3VyY2VzIGluIGEgc3lzdGVtIGlzIG5vdCBtdWNoLgoKU2F5IHRo YXQgSSB3YW50IHRvIHNwaW4gdXAgMjQgTklDIHF1ZXVlcyB3aXRoIG9uZSBNU0kgZWFjaCBvbiBl YWNoIGNvcmUKb24gbXkgMTI4YyBzeXN0ZW0uIFRoYXQncyBub3QgcG9zc2libGUgd2l0aCB0aGlz IHNlcmllcywgd2hpbGUgd2l0aCBhbgoxLTEgc3lzdGVtIGl0IHdvdWxkbid0IGJlIGFuIGlzc3Vl LgoKQ2xlYXJlciwgb3Igc3RpbGwgd2VpcmQ/Cgo+Cj4+Cj4+ID4gUmVnYXJkaW5nIE5JQ3Mgd2hp Y2ggc3VwcG9ydCBhIGxhcmdlIG51bWJlciBvZiBxdWV1ZXMsIHRoZSBkcml2ZXIKPj4gPiB3aWxs IHR5cGljYWxseSBlbmFibGUgb25seSBvbmUgcXVldWUgcGVyLWNvcmUgYW5kIHNldCB0aGUgYWZm aW5pdHkgdG8KPj4gPiBzZXBhcmF0ZSBjb3Jlcy4gV2UgaGF2ZSB1c2VyLXNwYWNlIGRhdGEgcGxh bmUgYXBwbGljYXRpb25zIGJhc2VkCj4+ID4gb24gRFBESyB3aGljaCBhcmUgY2FwYWJsZSBvZiB1 c2luZyBhIGxhcmdlIG51bWJlciBvZiBOSUMgcXVldWVzCj4+ID4gYnV0IHRoZXNlIGFwcGxpY2F0 aW9ucyBhcmUgcG9sbGluZyBiYXNlZCBhbmQgZG9uJ3QgdXNlIE1TSXMuCj4+Cj4+IFRoYXQncyBv bmUgc2FtcGxlIHBvaW50LCBhbmQgY2xlYXJseSBub3QgdGhlIG9ubHkgb25lLiBUaGVyZSBhcmUg Km1hbnkqCj4+IGRpZmZlcmVudCB1c2FnZSBtb2RlbHMuIEp1c3QgYmVjYXVzZSB5b3UgKmFzc2ln biogTVNJLCBkb2Vzbid0IG1lYW4gdGhleQo+PiBhcmUgZmlyaW5nIGFsbCB0aGUgdGltZS4KPj4K Pj4gSSBjYW4gc2hvdyB5b3UgYSBjb3VwbGUgb2YgbmV0d29ya2luZyBzZXR1cHMgd2hlcmUgdGhp cyBpcyBjbGVhcmx5IG5vdAo+PiBlbm91Z2guIEVhY2ggY29yZSBoYXMgYSBsYXJnZSBudW1iZXIg b2YgUW9TIHF1ZXVlcywgYW5kIGVhY2ggcXVldWUgd291bGQKPj4gdmVyeSBtdWNoIGxpa2UgdG8g aGF2ZSBhIGRlZGljYXRlZCBNU0kuCj4+Cj4+ID4+ID4gV2hlbiB3ZSBlbmNvdW50ZXIgYSBzeXN0 ZW0gcmVxdWlyaW5nIGEgbGFyZ2UgbnVtYmVyIG9mIE1TSXMsCj4+ID4+ID4gd2UgY2FuIGVpdGhl cjoKPj4gPj4gPiAxKSBFeHRlbmQgdGhlIEFJQSBzcGVjIHRvIHN1cHBvcnQgZ3JlYXRlciB0aGFu IDIwNDcgSURzCj4+ID4+ID4gMikgUmUtdGhpbmsgdGhlIGFwcHJvYWNoIGluIHRoZSBJTVNJQyBk cml2ZXIKPj4gPj4gPgo+PiA+PiA+IFRoZSBjaG9pY2UgYmV0d2VlbiAjMSBhbmQgIzIgYWJvdmUg ZGVwZW5kcyBvbiB0aGUKPj4gPj4gPiBndWFyYW50ZWVzIHdlIHdhbnQgZm9yIGlycV9zZXRfYWZm aW5pdHkoKS4KPj4gPj4KPj4gPj4gVGhlIGlycV9zZXRfYWZmaW5pdHkoKSBiZWhhdmlvciBpcyBi ZXR0ZXIgd2l0aCB0aGlzIHNlcmllcywgYnV0IEkgdGhpbmsKPj4gPj4gdGhlIG90aGVyIGRvd25z aWRlczogbnVtYmVyIG9mIGF2YWlsYWJsZSBpbnRlcnJ1cHQgc291cmNlcywgYW5kIElQSQo+PiA+ PiBicm9hZGNhc3QgYXJlIHdvcnNlLgo+PiA+Cj4+ID4gVGhlIElQSSBvdmVyaGVhZCBpbiB0aGUg YXBwcm9hY2ggeW91IGFyZSBzdWdnZXN0aW5nIHdpbGwgYmUKPj4gPiBldmVuIGJhZCBjb21wYXJl ZCB0byB0aGUgSVBJIG92ZXJoZWFkIG9mIHRoZSBjdXJyZW50IGFwcHJvYWNoCj4+ID4gYmVjYXVz ZSB3ZSB3aWxsIGVuZC11cCBkb2luZyBJUEkgdXBvbiBldmVyeSBpcnFfc2V0X2FmZmluaXR5KCkK Pj4gPiBpbiB0aGUgc3VnZ2VzdGVkIGFwcHJvYWNoIGNvbXBhcmVkIHRvIGRvaW5nIElQSSB1cG9u IGV2ZXJ5Cj4+ID4gbWFzay91bm1hc2sgaW4gdGhlIGN1cnJlbnQgYXBwcm9hY2guCj4+Cj4+IEFn YWluLCB2ZXJ5IHdvcmtsb2FkIGRlcGVuZGVudC4KPj4KPj4gVGhpcyBzZXJpZXMgZG9lcyBJUEkg YnJvYWRjYXN0IG9uIG1hc2tpbmcvdW5tYXNraW5nLCB3aGljaCBtZWFucyB0aGF0Cj4+IGNvcmVz IHRoYXQgZG9uJ3QgY2FyZSBnZXQgaW50ZXJydXB0ZWQgYmVjYXVzZSwgc2F5LCBhIG5ldHdvcmsg cXVldWUtcGFpcgo+PiBpcyBzZXR1cCBvbiBhbm90aGVyIGNvcmUuCj4+Cj4+IFNvbWUgd29ya2xv YWRzIG5ldmVyIGNoYW5nZSB0aGUgaXJxIGFmZmluaXR5Lgo+Cj4gVGhlcmUgYXJlIHZhcmlvdXMg ZXZlbnRzIHdoaWNoIGlycSBhZmZpbml0eSBzdWNoIGFzIGlycSBiYWxhbmNlLAo+IENQVSBob3Rw bHVnLCBzeXN0ZW0gc3VzcGVuZCwgZXRjLgo+Cj4gQWxzbywgdGhlIDEtMSBhcHByb2FjaCBkb2Vz IElQSSB1cG9uIHNldF9hZmZpbml0eSwgbWFzayBhbmQKPiB1bm1hc2sgd2hlcmVhcyB0aGUgMS1u IGFwcHJvYWNoIGRvZXMgSVBJIG9ubHkgdXBvbiBtYXNrCj4gYW5kIHVubWFzay4KCkFuIGltcG9y dGFudCBkaXN0aW5jdGlvbjsgV2hlbiB5b3Ugc2F5IElQSSBvbiBtYXNrL3VubWFzayBpdCBpcyBh CmJyb2FkY2FzdCBJUEkgdG8gKmFsbCogY29yZXMsIHdoaWNoIGlzIHByZXR0eSBpbnN0cnVzaXZl LgoKVGhlIDEtMSB2YXJpYW50IGRvZXMgYW4gSVBJIHRvIGEgKm9uZSogdGFyZ2V0IGNvcmUuCgo+ PiBJJ20ganVzdCBwb2ludGluZyBvdXQgdGhhdCB0aGVyZSBhcmUgcHJvL2NvbnMgd2l0aCBib3Ro IHZhcmlhbnRzLgo+Pgo+PiA+IFRoZSBiaWdnZXN0IGFkdmFudGFnZSBvZiB0aGUgY3VycmVudCBh cHByb2FjaCBpcyBhIHJlbGlhYmxlCj4+ID4gaXJxX3NldF9hZmZpbml0eSgpIHdoaWNoIGlzIGEg dmVyeSB2YWx1YWJsZSB0aGluZyB0byBoYXZlLgo+Pgo+PiAuLi5hbmQgSSdtIGFyZ3VpbmcgdGhh dCB3ZSdyZSBwYXlpbmcgYSBiaWcgcHJpY2UgZm9yIHRoYXQuCj4+Cj4+ID4gQVJNIHN5c3RlbXMg ZWFzaWx5IHN1cHBvcnQgYSBsYXJnZSBudW1iZXIgb2YgTFBJcyBwZXItY29yZS4KPj4gPiBGb3Ig ZXhhbXBsZSwgR0lDLTcwMCBzdXBwb3J0cyA1NjAwMCBMUElzIHBlci1jb3JlLgo+PiA+IChSZWZl ciwgaHR0cHM6Ly9kZXZlbG9wZXIuYXJtLmNvbS9kb2N1bWVudGF0aW9uLzEwMTUxNi8wMzAwL0Fi b3V0LXRoZS1HSUMtNzAwL0ZlYXR1cmVzKQo+Pgo+PiBZZWFoLCBidXQgdGhpcyBpcyBub3QgdGhl IEdJQy4gVGhpcyBpcyBzb21ldGhpbmcgdGhhdCBsb29rcyBtb3JlIGxpa2UKPj4gdGhlIHg4NiB3 b3JsZC4gV2UnbGwgYmUgc3R1Y2sgd2l0aCBhIGxvdCBvZiBpbXBsZW1lbnRhdGlvbnMgd2l0aCBB SUEgMS4wCj4+IHNwZWMsIGFuZCBtYW55IGNvcmVzLgo+Cj4gV2VsbCwgUklTQy1WIEFJQSBpcyBu ZWlnaGVyIEFSTSBHSUcgbm90IHg4NiBBUElDLiBBbGwgSSBhbSBzYXlpbmcKPiBpcyB0aGF0IHRo ZXJlIGFyZSBzeXN0ZW1zIHdpdGggbGFyZ2UgbnVtYmVyIHBlci1jb3JlIGludGVycnVwdCBJRHMK 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(UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1697831128; bh=w20LFURbBMrbFbfKlNvLx4G7zOkHbNQac0n02X5DHnM=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=Sdep1+c0KL9zzmvUTGS83P2istPzUonpp11T0DdFI6SHHLScZ6DhvKrFS0UYUGmBK RBFaPWCWbtAbkjjEOKgJvx3/fQK2NsiundaEis3NV03NyrGHx02epDH2wXMc0D47PV wJu8fvKyo5+o3OfTTvPnfzV83Yn/vwmFot7G0csBVMdYyigTdhSAm3+w42adoGJhDU OiHR+y1wPGo4oRs5l8E0M0+AS6lYRQKdFMGV7ofyLKZ7taZ6Q4D8aOEc4/KlaDybWG B90L+ABPi4UmmvHH11Xm4q6sqBArpWxet8fyS4VjNljLIAQP4M6qbPuhHr1mGh8ZSj HF6mErwfFxZzg== From: =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= To: Anup Patel Cc: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v10 00/15] Linux RISC-V AIA Support In-Reply-To: References: <20231003044403.1974628-1-apatel@ventanamicro.com> <87o7gu7mo9.fsf@all.your.base.are.belong.to.us> <87h6mlbryy.fsf@all.your.base.are.belong.to.us> <87o7gtpdb4.fsf@all.your.base.are.belong.to.us> <87v8b1i72s.fsf@all.your.base.are.belong.to.us> Date: Fri, 20 Oct 2023 21:45:25 +0200 Message-ID: <875y31cc2y.fsf@all.your.base.are.belong.to.us> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Anup Patel writes: > On Fri, Oct 20, 2023 at 10:07=E2=80=AFPM Bj=C3=B6rn T=C3=B6pel wrote: >> >> Anup Patel writes: >> >> > On Fri, Oct 20, 2023 at 8:10=E2=80=AFPM Bj=C3=B6rn T=C3=B6pel wrote: >> >> >> >> Anup Patel writes: >> >> >> >> > On Fri, Oct 20, 2023 at 2:17=E2=80=AFPM Bj=C3=B6rn T=C3=B6pel wrote: >> >> >> >> >> >> Thanks for the quick reply! >> >> >> >> >> >> Anup Patel writes: >> >> >> >> >> >> > On Thu, Oct 19, 2023 at 7:13=E2=80=AFPM Bj=C3=B6rn T=C3=B6pel wrote: >> >> >> >> >> >> >> >> Hi Anup, >> >> >> >> >> >> >> >> Anup Patel writes: >> >> >> >> >> >> >> >> > The RISC-V AIA specification is ratified as-per the RISC-V in= ternational >> >> >> >> > process. The latest ratified AIA specifcation can be found at: >> >> >> >> > https://github.com/riscv/riscv-aia/releases/download/1.0/risc= v-interrupts-1.0.pdf >> >> >> >> > >> >> >> >> > At a high-level, the AIA specification adds three things: >> >> >> >> > 1) AIA CSRs >> >> >> >> > - Improved local interrupt support >> >> >> >> > 2) Incoming Message Signaled Interrupt Controller (IMSIC) >> >> >> >> > - Per-HART MSI controller >> >> >> >> > - Support MSI virtualization >> >> >> >> > - Support IPI along with virtualization >> >> >> >> > 3) Advanced Platform-Level Interrupt Controller (APLIC) >> >> >> >> > - Wired interrupt controller >> >> >> >> > - In MSI-mode, converts wired interrupt into MSIs (i.e. MS= I generator) >> >> >> >> > - In Direct-mode, injects external interrupts directly int= o HARTs >> >> >> >> >> >> >> >> Thanks for working on the AIA support! I had a look at the seri= es, and >> >> >> >> have some concerns about interrupt ID abstraction. >> >> >> >> >> >> >> >> A bit of background, for readers not familiar with the AIA deta= ils. >> >> >> >> >> >> >> >> IMSIC allows for 2047 unique MSI ("msi-irq") sources per hart, = and >> >> >> >> each MSI is dedicated to a certain hart. The series takes the a= pproach >> >> >> >> to say that there are, e.g., 2047 interrupts ("lnx-irq") global= ly. >> >> >> >> Each lnx-irq consists of #harts * msi-irq -- a slice -- and in = the >> >> >> >> slice only *one* msi-irq is acutally used. >> >> >> >> >> >> >> >> This scheme makes affinity changes more robust, because the int= errupt >> >> >> >> sources on "other" harts are pre-allocated. On the other hand it >> >> >> >> requires to propagate irq masking to other harts via IPIs (this= is >> >> >> >> mostly done up setup/tear down). It's also wasteful, because ms= i-irqs >> >> >> >> are hogged, and cannot be used. >> >> >> >> >> >> >> >> Contemporary storage/networking drivers usually uses queues per= core >> >> >> >> (or a sub-set of cores). The current scheme wastes a lot of msi= -irqs. >> >> >> >> If we instead used a scheme where "msi-irq =3D=3D lnx-irq", ins= tead of >> >> >> >> "lnq-irq =3D {hart 0;msi-irq x , ... hart N;msi-irq x}", there = would be >> >> >> >> a lot MSIs for other users. 1-1 vs 1-N. E.g., if a storage devi= ce >> >> >> >> would like to use 5 queues (5 cores) on a 128 core system, the = current >> >> >> >> scheme would consume 5 * 128 MSIs, instead of just 5. >> >> >> >> >> >> >> >> On the plus side: >> >> >> >> * Changing interrupts affinity will never fail, because the int= errupts >> >> >> >> on each hart is pre-allocated. >> >> >> >> >> >> >> >> On the negative side: >> >> >> >> * Wasteful interrupt usage, and a system can potientially "run = out" of >> >> >> >> interrupts. Especially for many core systems. >> >> >> >> * Interrupt masking need to proagate to harts via IPIs (there's= no >> >> >> >> broadcast csr in IMSIC), and a more complex locking scheme IM= SIC >> >> >> >> >> >> >> >> Summary: >> >> >> >> The current series caps the number of global interrupts to maxi= mum >> >> >> >> 2047 MSIs for all cores (whole system). A better scheme, IMO, w= ould be >> >> >> >> to expose 2047 * #harts unique MSIs. >> >> >> >> >> >> >> >> I think this could simplify/remove(?) the locking as well. >> >> >> > >> >> >> > Exposing 2047 * #harts unique MSIs has multiple issues: >> >> >> > 1) The irq_set_affinity() does not work for MSIs because each >> >> >> > IRQ is not tied to a particular HART. This means we can't >> >> >> > balance the IRQ processing load among HARTs. >> >> >> >> >> >> Yes, you can balance. In your code, each *active* MSI is still >> >> >> bound/active to a specific hard together with the affinity mask. I= n an >> >> >> 1-1 model you would still need to track the affinity mask, but the >> >> >> irq_set_affinity() would be different. It would try to allocate a = new >> >> >> MSI from the target CPU, and then switch to having that MSI active. >> >> >> >> >> >> That's what x86 does AFAIU, which is also constrained by the # of >> >> >> available MSIs. >> >> >> >> >> >> The downside, as I pointed out, is that the set affinity action can >> >> >> fail for a certain target CPU. >> >> > >> >> > Yes, irq_set_affinity() can fail for the suggested approach plus for >> >> > RISC-V AIA, one HART does not have access to other HARTs >> >> > MSI enable/disable bits so the approach will also involve IPI. >> >> >> >> Correct, but the current series does a broadcast to all cores, where = the >> >> 1-1 approach is at most an IPI to a single core. >> >> >> >> 128+c machines are getting more common, and you have devices that you >> >> bring up/down on a per-core basis. Broadcasting IPIs to all cores, wh= en >> >> dealing with a per-core activity is a pretty noisy neighbor. >> > >> > Broadcast IPI in the current approach is only done upon MSI mask/unmask >> > operation. It is not done upon set_affinity() of interrupt handling. >> >> I'm aware. We're on the same page here. >> >> >> >> >> This could be fixed in the existing 1-n approach, by not require to s= ync >> >> the cores that are not handling the MSI in question. "Lazy disable" >> > >> > Incorrect. The approach you are suggesting involves an IPI upon every >> > irq_set_affinity(). This is because a HART can only enable it's own >> > MSI ID so when an IRQ is moved to from HART A to HART B with >> > a different ID X on HART B then we will need an IPI in irq_set_affinit= () >> > to enable ID X on HART B. >> >> Yes, the 1-1 approach will require an IPI to one target cpu on affinity >> changes, and similar on mask/unmask. >> >> The 1-n approach, require no-IPI on affinity changes (nice!), but IPI >> broadcast to all cores on mask/unmask (not so nice). >> >> >> >> My concern is interrupts become a scarce resource with this >> >> >> implementation, but maybe my view is incorrect. I've seen bare-met= al >> >> >> x86 systems (no VMs) with ~200 cores, and ~2000 interrupts, but ma= ybe >> >> >> that is considered "a lot of interrupts". >> >> >> >> >> >> As long as we don't get into scenarios where we're running out of >> >> >> interrupts, due to the software design. >> >> >> >> >> > >> >> > The current approach is simpler and ensures irq_set_affinity >> >> > always works. The limit of max 2047 IDs is sufficient for many >> >> > systems (if not all). >> >> >> >> Let me give you another view. On a 128c system each core has ~16 uniq= ue >> >> interrupts for disposal. E.g. the Intel E800 NIC has more than 2048 >> >> network queue pairs for each PF. >> > >> > Clearly, this example is a hypothetical and represents a poorly >> > designed platform. >> > >> > Having just 16 IDs per-Core is a very poor design choice. In fact, the >> > Server SoC spec mandates a minimum 255 IDs. >> >> You are misreading. A 128c system with 2047 MSIs per-core, will only >> have 16 *per-core unique* (2047/128) interrupts with the current series. >> >> I'm not saying that each IMSIC has 16 IDs, I'm saying that in a 128c >> system with the maximum amount of MSIs possible in the spec, you'll end >> up with 16 *unique* interrupts per core. > > -ENOPARSE > > I don't see how this applies to the current approach because we treat > MSI ID space as global across cores so if a system has 2047 MSIs > per-core then we have 2047 MSIs across all cores. Ok, I'll try again! :-) Let's assume that each core in the 128c system has some per-core resources, say a two NIC queue pairs, and a storage queue pair. This will consume, e.g., 2*2 + 2 (6) MSI sources from the global namespace. If each core does this it'll be 6*128 MSI sources of the global namespace. The maximum number of "privates" MSI sources a core can utilize is 16. I'm trying (it's does seem to go that well ;-)) to point out that it's only 16 unique sources per core. For, say, a 256 core system it would be 8. 2047 MSI sources in a system is not much. Say that I want to spin up 24 NIC queues with one MSI each on each core on my 128c system. That's not possible with this series, while with an 1-1 system it wouldn't be an issue. Clearer, or still weird? > >> >> > Regarding NICs which support a large number of queues, the driver >> > will typically enable only one queue per-core and set the affinity to >> > separate cores. We have user-space data plane applications based >> > on DPDK which are capable of using a large number of NIC queues >> > but these applications are polling based and don't use MSIs. >> >> That's one sample point, and clearly not the only one. There are *many* >> different usage models. Just because you *assign* MSI, doesn't mean they >> are firing all the time. >> >> I can show you a couple of networking setups where this is clearly not >> enough. Each core has a large number of QoS queues, and each queue would >> very much like to have a dedicated MSI. >> >> >> > When we encounter a system requiring a large number of MSIs, >> >> > we can either: >> >> > 1) Extend the AIA spec to support greater than 2047 IDs >> >> > 2) Re-think the approach in the IMSIC driver >> >> > >> >> > The choice between #1 and #2 above depends on the >> >> > guarantees we want for irq_set_affinity(). >> >> >> >> The irq_set_affinity() behavior is better with this series, but I thi= nk >> >> the other downsides: number of available interrupt sources, and IPI >> >> broadcast are worse. >> > >> > The IPI overhead in the approach you are suggesting will be >> > even bad compared to the IPI overhead of the current approach >> > because we will end-up doing IPI upon every irq_set_affinity() >> > in the suggested approach compared to doing IPI upon every >> > mask/unmask in the current approach. >> >> Again, very workload dependent. >> >> This series does IPI broadcast on masking/unmasking, which means that >> cores that don't care get interrupted because, say, a network queue-pair >> is setup on another core. >> >> Some workloads never change the irq affinity. > > There are various events which irq affinity such as irq balance, > CPU hotplug, system suspend, etc. > > Also, the 1-1 approach does IPI upon set_affinity, mask and > unmask whereas the 1-n approach does IPI only upon mask > and unmask. An important distinction; When you say IPI on mask/unmask it is a broadcast IPI to *all* cores, which is pretty instrusive. The 1-1 variant does an IPI to a *one* target core. >> I'm just pointing out that there are pro/cons with both variants. >> >> > The biggest advantage of the current approach is a reliable >> > irq_set_affinity() which is a very valuable thing to have. >> >> ...and I'm arguing that we're paying a big price for that. >> >> > ARM systems easily support a large number of LPIs per-core. >> > For example, GIC-700 supports 56000 LPIs per-core. >> > (Refer, https://developer.arm.com/documentation/101516/0300/About-the-= GIC-700/Features) >> >> Yeah, but this is not the GIC. This is something that looks more like >> the x86 world. We'll be stuck with a lot of implementations with AIA 1.0 >> spec, and many cores. > > Well, RISC-V AIA is neigher ARM GIG not x86 APIC. All I am saying > is that there are systems with large number per-core interrupt IDs > for handling MSIs. Yes, and while that is nice, it's not what IMSIC is. Now, back to the weekend for real! ;-) (https://xkcd.com/386/) Bj=C3=B6rn