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Thu, 19 Aug 2021 08:15:24 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mGdCq-007gSV-Oz for linux-arm-kernel@lists.infradead.org; Thu, 19 Aug 2021 08:15:22 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6ADDA61101; Thu, 19 Aug 2021 08:15:20 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mGdCo-005vNY-D7; Thu, 19 Aug 2021 09:15:18 +0100 Date: Thu, 19 Aug 2021 09:15:17 +0100 Message-ID: <875yw1sve2.wl-maz@kernel.org> From: Marc Zyngier To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, oupton@google.com, will@kernel.org Subject: Re: [PATCH] arm64: initialize all of CNTHCTL_EL2 In-Reply-To: <20210818161535.52786-1-mark.rutland@arm.com> References: <20210818161535.52786-1-mark.rutland@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, oupton@google.com, will@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210819_011520_879507_0AB5FA1F X-CRM114-Status: GOOD ( 27.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 18 Aug 2021 17:15:35 +0100, Mark Rutland wrote: > > In __init_el2_timers we initialize CNTHCTL_EL2.{EL1PCEN,EL1PCTEN} with a > RMW sequence, leaving all other bits UNKNOWN. > > In general, we should initialize all bits in a register rather than > using an RMW sequence, since most bits are UNKNOWN out of reset, and as > new bits are added to the reigster their reset value might not result in > expected behaviour. > > In the case of CNTHCTL_EL2, FEAT_ECV added a number of new control bits > in previously RES0 bits, which reset to UNKNOWN values, and may cause > issues for EL1 and EL0: > > * CNTHCTL_EL2.ECV enables the CNTPOFF_EL2 offset (which itself resets to > an UNKNOWN value) at EL0 and EL1. Since the offset could reset to > distinct values across CPUs, when the control bit resets to 1 this > could break timekeeping generally. > > * CNTHCTL_EL2.{EL1TVT,EL1TVCT} trap EL0 and EL1 accesses to the EL1 > virtual timer/counter registers to EL2. When reset to 1, this could > cause unexpected traps to EL2. > > Initializing these bits to zero avoids these problems, and all other > bits in CNPTOFF_EL2 other than EL1PCEN and EL1PCTEN can safely be reset > to zero. > > This patch ensures we initialize CNTHCTL_EL2 accordingly, only setting > EL1PCEN and EL1PCTEN, and setting all other bits to zero. > > Signed-off-by: Mark Rutland > Cc: Catalin Marinas > Cc: Marc Zyngier > Cc: Oliver Upton > Cc: Will Deacon > --- > arch/arm64/include/asm/el2_setup.h | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h > index 21fa330f498dd..b83fb24954b77 100644 > --- a/arch/arm64/include/asm/el2_setup.h > +++ b/arch/arm64/include/asm/el2_setup.h > @@ -33,8 +33,7 @@ > * EL2. > */ > .macro __init_el2_timers > - mrs x0, cnthctl_el2 > - orr x0, x0, #3 // Enable EL1 physical timers > + mov x0, #3 // Enable EL1 physical timers > msr cnthctl_el2, x0 > msr cntvoff_el2, xzr // Clear virtual offset > .endm With the typo spotted by Oliver fixed: Acked-by: Marc Zyngier M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel