From mboxrd@z Thu Jan 1 00:00:00 1970 From: Fabiano Rosas Date: Fri, 06 Aug 2021 20:45:19 +0000 Subject: Re: [PATCH v1 30/55] KVM: PPC: Book3S HV P9: Only execute mtSPR if the value changed Message-Id: <875ywiti8w.fsf@linux.ibm.com> List-Id: References: <20210726035036.739609-1-npiggin@gmail.com> <20210726035036.739609-31-npiggin@gmail.com> In-Reply-To: <20210726035036.739609-31-npiggin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Nicholas Piggin , kvm-ppc@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, Nicholas Piggin Nicholas Piggin writes: > Keep better track of the current SPR value in places where > they are to be loaded with a new context, to reduce expensive > mtSPR operations. > > -73 cycles (7354) POWER9 virt-mode NULL hcall > > Signed-off-by: Nicholas Piggin Reviewed-by: Fabiano Rosas > --- > arch/powerpc/kvm/book3s_hv.c | 64 ++++++++++++++++++++++-------------- > 1 file changed, 39 insertions(+), 25 deletions(-) > > diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c > index 0d97138e6fa4..56429b53f4dc 100644 > --- a/arch/powerpc/kvm/book3s_hv.c > +++ b/arch/powerpc/kvm/book3s_hv.c > @@ -4009,19 +4009,28 @@ static void switch_pmu_to_host(struct kvm_vcpu *vcpu, > } > } > > -static void load_spr_state(struct kvm_vcpu *vcpu) > +static void load_spr_state(struct kvm_vcpu *vcpu, > + struct p9_host_os_sprs *host_os_sprs) > { > - mtspr(SPRN_DSCR, vcpu->arch.dscr); > - mtspr(SPRN_IAMR, vcpu->arch.iamr); > - mtspr(SPRN_PSPB, vcpu->arch.pspb); > - mtspr(SPRN_FSCR, vcpu->arch.fscr); > mtspr(SPRN_TAR, vcpu->arch.tar); > mtspr(SPRN_EBBHR, vcpu->arch.ebbhr); > mtspr(SPRN_EBBRR, vcpu->arch.ebbrr); > mtspr(SPRN_BESCR, vcpu->arch.bescr); > - mtspr(SPRN_TIDR, vcpu->arch.tid); > - mtspr(SPRN_AMR, vcpu->arch.amr); > - mtspr(SPRN_UAMOR, vcpu->arch.uamor); > + > + if (!cpu_has_feature(CPU_FTR_ARCH_31)) > + mtspr(SPRN_TIDR, vcpu->arch.tid); > + if (host_os_sprs->iamr != vcpu->arch.iamr) > + mtspr(SPRN_IAMR, vcpu->arch.iamr); > + if (host_os_sprs->amr != vcpu->arch.amr) > + mtspr(SPRN_AMR, vcpu->arch.amr); > + if (vcpu->arch.uamor != 0) > + mtspr(SPRN_UAMOR, vcpu->arch.uamor); > + if (host_os_sprs->fscr != vcpu->arch.fscr) > + mtspr(SPRN_FSCR, vcpu->arch.fscr); > + if (host_os_sprs->dscr != vcpu->arch.dscr) > + mtspr(SPRN_DSCR, vcpu->arch.dscr); > + if (vcpu->arch.pspb != 0) > + mtspr(SPRN_PSPB, vcpu->arch.pspb); > > /* > * DAR, DSISR, and for nested HV, SPRGs must be set with MSR[RI] > @@ -4036,28 +4045,31 @@ static void load_spr_state(struct kvm_vcpu *vcpu) > > static void store_spr_state(struct kvm_vcpu *vcpu) > { > - vcpu->arch.ctrl = mfspr(SPRN_CTRLF); > - > - vcpu->arch.iamr = mfspr(SPRN_IAMR); > - vcpu->arch.pspb = mfspr(SPRN_PSPB); > - vcpu->arch.fscr = mfspr(SPRN_FSCR); > vcpu->arch.tar = mfspr(SPRN_TAR); > vcpu->arch.ebbhr = mfspr(SPRN_EBBHR); > vcpu->arch.ebbrr = mfspr(SPRN_EBBRR); > vcpu->arch.bescr = mfspr(SPRN_BESCR); > - vcpu->arch.tid = mfspr(SPRN_TIDR); > + > + if (!cpu_has_feature(CPU_FTR_ARCH_31)) > + vcpu->arch.tid = mfspr(SPRN_TIDR); > + vcpu->arch.iamr = mfspr(SPRN_IAMR); > vcpu->arch.amr = mfspr(SPRN_AMR); > vcpu->arch.uamor = mfspr(SPRN_UAMOR); > + vcpu->arch.fscr = mfspr(SPRN_FSCR); > vcpu->arch.dscr = mfspr(SPRN_DSCR); > + vcpu->arch.pspb = mfspr(SPRN_PSPB); > + > + vcpu->arch.ctrl = mfspr(SPRN_CTRLF); > } > > static void save_p9_host_os_sprs(struct p9_host_os_sprs *host_os_sprs) > { > - host_os_sprs->dscr = mfspr(SPRN_DSCR); > - host_os_sprs->tidr = mfspr(SPRN_TIDR); > + if (!cpu_has_feature(CPU_FTR_ARCH_31)) > + host_os_sprs->tidr = mfspr(SPRN_TIDR); > host_os_sprs->iamr = mfspr(SPRN_IAMR); > host_os_sprs->amr = mfspr(SPRN_AMR); > host_os_sprs->fscr = mfspr(SPRN_FSCR); > + host_os_sprs->dscr = mfspr(SPRN_DSCR); > } > > /* vcpu guest regs must already be saved */ > @@ -4066,18 +4078,20 @@ static void restore_p9_host_os_sprs(struct kvm_vcpu *vcpu, > { > mtspr(SPRN_SPRG_VDSO_WRITE, local_paca->sprg_vdso); > > - mtspr(SPRN_PSPB, 0); > - mtspr(SPRN_UAMOR, 0); > - > - mtspr(SPRN_DSCR, host_os_sprs->dscr); > - mtspr(SPRN_TIDR, host_os_sprs->tidr); > - mtspr(SPRN_IAMR, host_os_sprs->iamr); > - > + if (!cpu_has_feature(CPU_FTR_ARCH_31)) > + mtspr(SPRN_TIDR, host_os_sprs->tidr); > + if (host_os_sprs->iamr != vcpu->arch.iamr) > + mtspr(SPRN_IAMR, host_os_sprs->iamr); > + if (vcpu->arch.uamor != 0) > + mtspr(SPRN_UAMOR, 0); > if (host_os_sprs->amr != vcpu->arch.amr) > mtspr(SPRN_AMR, host_os_sprs->amr); > - > if (host_os_sprs->fscr != vcpu->arch.fscr) > mtspr(SPRN_FSCR, host_os_sprs->fscr); > + if (host_os_sprs->dscr != vcpu->arch.dscr) > + mtspr(SPRN_DSCR, host_os_sprs->dscr); > + if (vcpu->arch.pspb != 0) > + mtspr(SPRN_PSPB, 0); > > /* Save guest CTRL register, set runlatch to 1 */ > if (!(vcpu->arch.ctrl & 1)) > @@ -4169,7 +4183,7 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit, > #endif > mtspr(SPRN_VRSAVE, vcpu->arch.vrsave); > > - load_spr_state(vcpu); > + load_spr_state(vcpu, &host_os_sprs); > > if (kvmhv_on_pseries()) { > /* From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBBDFC4338F for ; Fri, 6 Aug 2021 20:46:00 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2BA3C60F0F for ; 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Fri, 6 Aug 2021 20:45:22 GMT Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9CA867805F; Fri, 6 Aug 2021 20:45:22 +0000 (GMT) Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E203578068; Fri, 6 Aug 2021 20:45:21 +0000 (GMT) Received: from localhost (unknown [9.211.46.8]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTPS; Fri, 6 Aug 2021 20:45:21 +0000 (GMT) From: Fabiano Rosas To: Nicholas Piggin , kvm-ppc@vger.kernel.org Subject: Re: [PATCH v1 30/55] KVM: PPC: Book3S HV P9: Only execute mtSPR if the value changed In-Reply-To: <20210726035036.739609-31-npiggin@gmail.com> References: <20210726035036.739609-1-npiggin@gmail.com> <20210726035036.739609-31-npiggin@gmail.com> Date: Fri, 06 Aug 2021 17:45:19 -0300 Message-ID: <875ywiti8w.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-GUID: ii6_keZEddzMnVM3hyJcfgfhdmU3fP5O X-Proofpoint-ORIG-GUID: J4j74svicpsIxTuWIkpJ0Jwk4Xr98E9N X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-06_06:2021-08-06, 2021-08-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 spamscore=0 mlxscore=0 malwarescore=0 priorityscore=1501 phishscore=0 adultscore=0 impostorscore=0 clxscore=1015 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108060136 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, Nicholas Piggin Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Nicholas Piggin writes: > Keep better track of the current SPR value in places where > they are to be loaded with a new context, to reduce expensive > mtSPR operations. > > -73 cycles (7354) POWER9 virt-mode NULL hcall > > Signed-off-by: Nicholas Piggin Reviewed-by: Fabiano Rosas > --- > arch/powerpc/kvm/book3s_hv.c | 64 ++++++++++++++++++++++-------------- > 1 file changed, 39 insertions(+), 25 deletions(-) > > diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c > index 0d97138e6fa4..56429b53f4dc 100644 > --- a/arch/powerpc/kvm/book3s_hv.c > +++ b/arch/powerpc/kvm/book3s_hv.c > @@ -4009,19 +4009,28 @@ static void switch_pmu_to_host(struct kvm_vcpu *vcpu, > } > } > > -static void load_spr_state(struct kvm_vcpu *vcpu) > +static void load_spr_state(struct kvm_vcpu *vcpu, > + struct p9_host_os_sprs *host_os_sprs) > { > - mtspr(SPRN_DSCR, vcpu->arch.dscr); > - mtspr(SPRN_IAMR, vcpu->arch.iamr); > - mtspr(SPRN_PSPB, vcpu->arch.pspb); > - mtspr(SPRN_FSCR, vcpu->arch.fscr); > mtspr(SPRN_TAR, vcpu->arch.tar); > mtspr(SPRN_EBBHR, vcpu->arch.ebbhr); > mtspr(SPRN_EBBRR, vcpu->arch.ebbrr); > mtspr(SPRN_BESCR, vcpu->arch.bescr); > - mtspr(SPRN_TIDR, vcpu->arch.tid); > - mtspr(SPRN_AMR, vcpu->arch.amr); > - mtspr(SPRN_UAMOR, vcpu->arch.uamor); > + > + if (!cpu_has_feature(CPU_FTR_ARCH_31)) > + mtspr(SPRN_TIDR, vcpu->arch.tid); > + if (host_os_sprs->iamr != vcpu->arch.iamr) > + mtspr(SPRN_IAMR, vcpu->arch.iamr); > + if (host_os_sprs->amr != vcpu->arch.amr) > + mtspr(SPRN_AMR, vcpu->arch.amr); > + if (vcpu->arch.uamor != 0) > + mtspr(SPRN_UAMOR, vcpu->arch.uamor); > + if (host_os_sprs->fscr != vcpu->arch.fscr) > + mtspr(SPRN_FSCR, vcpu->arch.fscr); > + if (host_os_sprs->dscr != vcpu->arch.dscr) > + mtspr(SPRN_DSCR, vcpu->arch.dscr); > + if (vcpu->arch.pspb != 0) > + mtspr(SPRN_PSPB, vcpu->arch.pspb); > > /* > * DAR, DSISR, and for nested HV, SPRGs must be set with MSR[RI] > @@ -4036,28 +4045,31 @@ static void load_spr_state(struct kvm_vcpu *vcpu) > > static void store_spr_state(struct kvm_vcpu *vcpu) > { > - vcpu->arch.ctrl = mfspr(SPRN_CTRLF); > - > - vcpu->arch.iamr = mfspr(SPRN_IAMR); > - vcpu->arch.pspb = mfspr(SPRN_PSPB); > - vcpu->arch.fscr = mfspr(SPRN_FSCR); > vcpu->arch.tar = mfspr(SPRN_TAR); > vcpu->arch.ebbhr = mfspr(SPRN_EBBHR); > vcpu->arch.ebbrr = mfspr(SPRN_EBBRR); > vcpu->arch.bescr = mfspr(SPRN_BESCR); > - vcpu->arch.tid = mfspr(SPRN_TIDR); > + > + if (!cpu_has_feature(CPU_FTR_ARCH_31)) > + vcpu->arch.tid = mfspr(SPRN_TIDR); > + vcpu->arch.iamr = mfspr(SPRN_IAMR); > vcpu->arch.amr = mfspr(SPRN_AMR); > vcpu->arch.uamor = mfspr(SPRN_UAMOR); > + vcpu->arch.fscr = mfspr(SPRN_FSCR); > vcpu->arch.dscr = mfspr(SPRN_DSCR); > + vcpu->arch.pspb = mfspr(SPRN_PSPB); > + > + vcpu->arch.ctrl = mfspr(SPRN_CTRLF); > } > > static void save_p9_host_os_sprs(struct p9_host_os_sprs *host_os_sprs) > { > - host_os_sprs->dscr = mfspr(SPRN_DSCR); > - host_os_sprs->tidr = mfspr(SPRN_TIDR); > + if (!cpu_has_feature(CPU_FTR_ARCH_31)) > + host_os_sprs->tidr = mfspr(SPRN_TIDR); > host_os_sprs->iamr = mfspr(SPRN_IAMR); > host_os_sprs->amr = mfspr(SPRN_AMR); > host_os_sprs->fscr = mfspr(SPRN_FSCR); > + host_os_sprs->dscr = mfspr(SPRN_DSCR); > } > > /* vcpu guest regs must already be saved */ > @@ -4066,18 +4078,20 @@ static void restore_p9_host_os_sprs(struct kvm_vcpu *vcpu, > { > mtspr(SPRN_SPRG_VDSO_WRITE, local_paca->sprg_vdso); > > - mtspr(SPRN_PSPB, 0); > - mtspr(SPRN_UAMOR, 0); > - > - mtspr(SPRN_DSCR, host_os_sprs->dscr); > - mtspr(SPRN_TIDR, host_os_sprs->tidr); > - mtspr(SPRN_IAMR, host_os_sprs->iamr); > - > + if (!cpu_has_feature(CPU_FTR_ARCH_31)) > + mtspr(SPRN_TIDR, host_os_sprs->tidr); > + if (host_os_sprs->iamr != vcpu->arch.iamr) > + mtspr(SPRN_IAMR, host_os_sprs->iamr); > + if (vcpu->arch.uamor != 0) > + mtspr(SPRN_UAMOR, 0); > if (host_os_sprs->amr != vcpu->arch.amr) > mtspr(SPRN_AMR, host_os_sprs->amr); > - > if (host_os_sprs->fscr != vcpu->arch.fscr) > mtspr(SPRN_FSCR, host_os_sprs->fscr); > + if (host_os_sprs->dscr != vcpu->arch.dscr) > + mtspr(SPRN_DSCR, host_os_sprs->dscr); > + if (vcpu->arch.pspb != 0) > + mtspr(SPRN_PSPB, 0); > > /* Save guest CTRL register, set runlatch to 1 */ > if (!(vcpu->arch.ctrl & 1)) > @@ -4169,7 +4183,7 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit, > #endif > mtspr(SPRN_VRSAVE, vcpu->arch.vrsave); > > - load_spr_state(vcpu); > + load_spr_state(vcpu, &host_os_sprs); > > if (kvmhv_on_pseries()) { > /*