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[83.165.45.250]) by smtp.gmail.com with ESMTPSA id l20sm3736801wrh.82.2021.01.13.05.47.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 05:47:48 -0800 (PST) From: Juan Quintela To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [RFC PATCH v6 04/11] hw/ssi: imx_spi: Reduce 'change_mask' variable scope In-Reply-To: <87im81gdig.fsf@secure.mitica> (Juan Quintela's message of "Wed, 13 Jan 2021 14:41:43 +0100") References: <20210112183529.2011863-1-f4bug@amsat.org> <20210112183529.2011863-5-f4bug@amsat.org> <87im81gdig.fsf@secure.mitica> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) Date: Wed, 13 Jan 2021 14:47:47 +0100 Message-ID: <875z41gd8c.fsf@secure.mitica> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=quintela@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.205.24.124; envelope-from=quintela@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.25, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: quintela@redhat.com Cc: Peter Maydell , Alistair Francis , Bin Meng , qemu-devel@nongnu.org, Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb , Bin Meng Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: iiB8zLPzV0tm Juan Quintela wrote: > Philippe Mathieu-Daud=C3=A9 wrote: >> Signed-off-by: Philippe Mathieu-Daud=C3=A9 > > I think this one is wrong. Wrong is a strong word. I mean that it changes behaviour and the commit message don't talk about changing behaviour. Later, Juan. > > >> --- >> hw/ssi/imx_spi.c | 3 +-- >> 1 file changed, 1 insertion(+), 2 deletions(-) >> >> diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c >> index 35ab33c0511..bcc535f2893 100644 >> --- a/hw/ssi/imx_spi.c >> +++ b/hw/ssi/imx_spi.c >> @@ -303,7 +303,6 @@ static void imx_spi_write(void *opaque, hwaddr offse= t, uint64_t value, >> { >> IMXSPIState *s =3D opaque; >> uint32_t index =3D offset >> 2; >> - uint32_t change_mask; >> =20 >> if (index >=3D ECSPI_MAX) { >> qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset = 0x%" >> @@ -313,7 +312,6 @@ static void imx_spi_write(void *opaque, hwaddr offse= t, uint64_t value, >> =20 >> trace_imx_spi_write(index, imx_spi_reg_name(index), value); >> =20 >> - change_mask =3D s->regs[index] ^ value; >> =20 >> switch (index) { >> case ECSPI_RXDATA: >> @@ -357,6 +355,7 @@ static void imx_spi_write(void *opaque, hwaddr offse= t, uint64_t value, >> } >> =20 >> if (imx_spi_channel_is_master(s)) { >> + uint32_t change_mask =3D s->regs[index] ^ value; >> int i; >> =20 >> /* We are in master mode */ > > The code does: > > change_mask =3D s->regs[index] ^ value; > > switch (index) { > > ... > > case ECSPI_CONREG: > s->regs[ECSPI_CONREG] =3D value; <<---- here > > if (!imx_spi_is_enabled(s)) { > /* device is disabled, so this is a reset */ > imx_spi_reset(DEVICE(s)); > return; > } > > if (imx_spi_channel_is_master(s)) { > int i; > >>>>> You are setting change_mask here. > > At this point, s->regs[index] has a new value in "here". > > Later, Juan.