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[124.171.97.196]) by smtp.gmail.com with ESMTPSA id z7sm10946534pga.6.2019.02.10.17.01.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:01:40 -0800 (PST) From: Daniel Axtens To: Sandipan Das , mpe@ellerman.id.au Subject: Re: [RFC PATCH 0/5] powerpc: sstep: Emulation test infrastructure In-Reply-To: References: Date: Mon, 11 Feb 2019 12:01:37 +1100 Message-ID: <875ztr3zpq.fsf@dja-thinkpad.axtens.net> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: naveen.n.rao@linux.ibm.com, linuxppc-dev@lists.ozlabs.org, paulus@samba.org, ravi.bangoria@linux.ibm.com Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Hi Sandipan, > This aims to add a test infrastructure for the in-kernel instruction > emulation code. This is currently limited to testing only the basic > integer operations and supports verification of the GPRs, LR, XER and > CR. > > There can be multiple test cases for each instruction. Each test case > has to be provided with the initial register state (in the form of a > struct pt_regs) and the 32-bit instruction to test. > > Apart from verifying the end result, problems with the behaviour of > certain instructions for things like setting certain bits in CR or > XER (which can also be processor dependent) can be identified. > For example, the newly introduced CA32 bit in XER, exclusive to P9 > CPUs as of now, was not being set when expected for some of the > arithmetic and shift instructions. With this infrastructure, it will > be easier to identify such problems and rectify them. The test cases > for the addc[.] instruction demonstrate this for different scenarios > where the CA and CA32 bits of XER should be set. > I forgot to mention this in my other emails - I think this is a really good idea, thank you for doing it. Regards, Daniel > Sandipan Das (5): > powerpc: Add bitmasks for D-form instruction fields > powerpc: Add bitmask for Rc instruction field > powerpc: sstep: Add instruction emulation selftests > powerpc: sstep: Add selftests for add[.] instruction > powerpc: sstep: Add selftests for addc[.] instruction > > arch/powerpc/Kconfig.debug | 5 + > arch/powerpc/include/asm/ppc-opcode.h | 5 + > arch/powerpc/lib/Makefile | 1 + > arch/powerpc/lib/exec_test_instr.S | 150 +++++++ > arch/powerpc/lib/sstep_tests.c | 564 ++++++++++++++++++++++++++ > 5 files changed, 725 insertions(+) > create mode 100644 arch/powerpc/lib/exec_test_instr.S > create mode 100644 arch/powerpc/lib/sstep_tests.c > > -- > 2.19.2