From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH 03/20] drm/i915/icl: Define DSI mode ctl register Date: Fri, 29 Jun 2018 14:51:39 +0300 Message-ID: <876021stdg.fsf@intel.com> References: <1529058084-31777-1-git-send-email-madhav.chauhan@intel.com> <1529058084-31777-4-git-send-email-madhav.chauhan@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id D993F6F092 for ; Fri, 29 Jun 2018 11:51:55 +0000 (UTC) In-Reply-To: <1529058084-31777-4-git-send-email-madhav.chauhan@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Madhav Chauhan , intel-gfx@lists.freedesktop.org Cc: paulo.r.zanoni@intel.com, rodrigo.vivi@intel.com List-Id: intel-gfx@lists.freedesktop.org T24gRnJpLCAxNSBKdW4gMjAxOCwgTWFkaGF2IENoYXVoYW4gPG1hZGhhdi5jaGF1aGFuQGludGVs LmNvbT4gd3JvdGU6Cj4gVGhpcyBwYXRjaCBkZWZpbmVzIERTSSBJTyBtb2RlIGNvbnRyb2wgcmVn aXN0ZXIgYW5kIGl0J3MgYml0cwo+IHVzZWQgd2hpbGUgZW5hYmxpbmcgSU8gcG93ZXIgZm9yIERT SS4KPgo+IFNpZ25lZC1vZmYtYnk6IE1hZGhhdiBDaGF1aGFuIDxtYWRoYXYuY2hhdWhhbkBpbnRl bC5jb20+Cj4gLS0tCj4gIGRyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfcmVnLmggfCA4ICsrKysr KysrCj4gIDEgZmlsZSBjaGFuZ2VkLCA4IGluc2VydGlvbnMoKykKPgo+IGRpZmYgLS1naXQgYS9k cml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1X3JlZy5oIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkx NV9yZWcuaAo+IGluZGV4IDU1ZWY1N2QuLjBkMjY4ZDEgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9n cHUvZHJtL2k5MTUvaTkxNV9yZWcuaAo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVf cmVnLmgKPiBAQCAtOTQ4Niw2ICs5NDg2LDE0IEBAIGVudW0gc2tsX3Bvd2VyX2dhdGUgewo+ICAj ZGVmaW5lIF9CWFRfTUlQSUNfUE9SVF9DVFJMCQkJCTB4NkI4QzAKPiAgI2RlZmluZSBCWFRfTUlQ SV9QT1JUX0NUUkwodGMpCV9NTUlPX01JUEkodGMsIF9CWFRfTUlQSUFfUE9SVF9DVFJMLCBfQlhU X01JUElDX1BPUlRfQ1RSTCkKPiAgCj4gKy8qIElDTCBEU0kgTU9ERSBjb250cm9sICovCj4gKyNk ZWZpbmUgX0lDTF9EU0lfSU9fTU9ERUNUTF8wCQkJCTB4NkIwOTQKPiArI2RlZmluZSBfSUNMX0RT SV9JT19NT0RFQ1RMXzEJCQkJMHg2Qjg5NAo+ICsjZGVmaW5lIElDTF9EU0lfSU9fTU9ERUNUTChw b3J0KQlfTU1JT19QT1JUKHBvcnQsCVwKPiArCQkJCQkJICAgIF9JQ0xfRFNJX0lPX01PREVDVExf MCwgXAo+ICsJCQkJCQkgICAgX0lDTF9EU0lfSU9fTU9ERUNUTF8xKQo+ICsjZGVmaW5lICBDT01C T19QSFlfTU9ERV9EU0kJCQkJKDEgPDwgMCkKPiArCgpJIHdvbmRlciBpZiBpdCB3b3VsZCBiZSB3 b3J0aCBpdCB0byBncm91cCBhbGwgSUNMIERTSSByZWdpc3RlciBpbiBvbmUKcGxhY2UgaW5zdGVh ZCBvZiBtaW5nbGluZyB3aXRoIHRoZSBCWVQvQlhUIHJlZ2lzdGVycy4KCkFnYWluLCBJJ2QgcHJl ZmVyIGl0IGlmIHRoZSByZWdpc3RlciBjb250ZW50IG1hY3JvcyB3ZXJlIGFsbCBzcGVjaWZpZWQK aW4gb25lIGdvLgoKRXZlbiBzbywKClJldmlld2VkLWJ5OiBKYW5pIE5pa3VsYSA8amFuaS5uaWt1 bGFAaW50ZWwuY29tPgoKCj4gICNkZWZpbmUgQlhUX1BfRFNJX1JFR1VMQVRPUl9DRkcJCQlfTU1J TygweDE2MDAyMCkKPiAgI2RlZmluZSAgU1RBUF9TRUxFQ1QJCQkJCSgxIDw8IDApCgotLSAKSmFu aSBOaWt1bGEsIEludGVsIE9wZW4gU291cmNlIEdyYXBoaWNzIENlbnRlcgpfX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpJbnRlbC1nZnggbWFpbGluZyBsaXN0 CkludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3Rv cC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK