From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alex =?utf-8?Q?Benn=C3=A9e?= Subject: Re: [PATCH v10 11/18] arm64/sve: Move read_zcr_features() out of cpufeature.h Date: Thu, 24 May 2018 11:12:09 +0100 Message-ID: <87603dtlae.fsf@linaro.org> References: <1527005119-6842-1-git-send-email-Dave.Martin@arm.com> <1527005119-6842-12-git-send-email-Dave.Martin@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-reply-to: <1527005119-6842-12-git-send-email-Dave.Martin@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Dave Martin Cc: Christoffer Dall , Ard Biesheuvel , Marc Zyngier , Catalin Marinas , Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org List-Id: kvmarm@lists.cs.columbia.edu CkRhdmUgTWFydGluIDxEYXZlLk1hcnRpbkBhcm0uY29tPiB3cml0ZXM6Cgo+IEhhdmluZyByZWFk X3pjcl9mZWF0dXJlcygpIGlubGluZSBpbiBjcHVmZWF0dXJlLmggcmVzdWx0cyBpbiB0aGF0Cj4g aGVhZGVyIHJlcXVpcmluZyAjaW5jbHVkZXMgd2hpY2ggbWFrZSBpdCBoYXJkIHRvIGluY2x1ZGUK PiA8YXNtL2Zwc2ltZC5oPiBlbHNld2hlcmUgd2l0aG91dCB0cmlnZ2VyaW5nIGhlYWRlciBpbmNs dXNpb24KPiBjeWNsZXMuCj4KPiBUaGlzIGlzIG5vdCBhIGhvdC1wYXRoIGZ1bmN0aW9uIGFuZCBh cmd1YWJseSBzaG91bGQgbm90IGJlIGluCj4gY3B1ZmVhdHVyZS5oIGluIHRoZSBmaXJzdCBwbGFj ZSwgc28gdGhpcyBwYXRjaCBtb3ZlcyBpdCB0bwo+IGZwc2ltZC5jLCBjb21waWxlZCBjb25kaXRp b25hbGx5IGlmIENPTkZJR19BUk02NF9TVkU9eS4KPgo+IFRoaXMgYWxsb3dzIHNvbWUgU1ZFLXJl bGF0ZWQgI2luY2x1ZGVzIHRvIGJlIGRyb3BwZWQgZnJvbQo+IGNwdWZlYXR1cmUuaCwgd2hpY2gg d2lsbCBlYXNlIGZ1dHVyZSBtYWludGVuYW5jZS4KPgo+IEEgY291cGxlIG9mIG1pc3NpbmcgI2lu Y2x1ZGVzIG9mIDxhc20vZnBzaW1kLmg+IGFyZSBleHBvc2VkIGJ5IHRoaXMKPiBjaGFuZ2UgdW5k ZXIgYXJjaC9hcm02NC8uICBUaGlzIHBhdGNoIGFkZHMgdGhlIG1pc3NpbmcgI2luY2x1ZGVzIGFz Cj4gbmVjZXNzYXJ5Lgo+Cj4gTm8gZnVuY3Rpb25hbCBjaGFuZ2UuCj4KPiBTaWduZWQtb2ZmLWJ5 OiBEYXZlIE1hcnRpbiA8RGF2ZS5NYXJ0aW5AYXJtLmNvbT4KPiBBY2tlZC1ieTogQ2F0YWxpbiBN YXJpbmFzIDxjYXRhbGluLm1hcmluYXNAYXJtLmNvbT4KPiBBY2tlZC1ieTogTWFyYyBaeW5naWVy IDxtYXJjLnp5bmdpZXJAYXJtLmNvbT4KClJldmlld2VkLWJ5OiBBbGV4IEJlbm7DqWUgPGFsZXgu YmVubmVlQGxpbmFyby5vcmc+Cgo+IC0tLQo+ICBhcmNoL2FybTY0L2luY2x1ZGUvYXNtL2NwdWZl YXR1cmUuaCB8IDI5IC0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tCj4gIGFyY2gvYXJtNjQv aW5jbHVkZS9hc20vZnBzaW1kLmggICAgIHwgIDIgKysKPiAgYXJjaC9hcm02NC9pbmNsdWRlL2Fz bS9wcm9jZXNzb3IuaCAgfCAgMSArCj4gIGFyY2gvYXJtNjQva2VybmVsL2Zwc2ltZC5jICAgICAg ICAgIHwgMjggKysrKysrKysrKysrKysrKysrKysrKysrKysrKwo+ICBhcmNoL2FybTY0L2tlcm5l bC9wdHJhY2UuYyAgICAgICAgICB8ICAxICsKPiAgNSBmaWxlcyBjaGFuZ2VkLCAzMiBpbnNlcnRp b25zKCspLCAyOSBkZWxldGlvbnMoLSkKPgo+IGRpZmYgLS1naXQgYS9hcmNoL2FybTY0L2luY2x1 ZGUvYXNtL2NwdWZlYXR1cmUuaCBiL2FyY2gvYXJtNjQvaW5jbHVkZS9hc20vY3B1ZmVhdHVyZS5o Cj4gaW5kZXggMDliMGYyYS4uMGE2YjcxMyAxMDA2NDQKPiAtLS0gYS9hcmNoL2FybTY0L2luY2x1 ZGUvYXNtL2NwdWZlYXR1cmUuaAo+ICsrKyBiL2FyY2gvYXJtNjQvaW5jbHVkZS9hc20vY3B1ZmVh dHVyZS5oCj4gQEAgLTExLDkgKzExLDcgQEAKPgo+ICAjaW5jbHVkZSA8YXNtL2NwdWNhcHMuaD4K PiAgI2luY2x1ZGUgPGFzbS9jcHV0eXBlLmg+Cj4gLSNpbmNsdWRlIDxhc20vZnBzaW1kLmg+Cj4g ICNpbmNsdWRlIDxhc20vaHdjYXAuaD4KPiAtI2luY2x1ZGUgPGFzbS9zaWdjb250ZXh0Lmg+Cj4g ICNpbmNsdWRlIDxhc20vc3lzcmVnLmg+Cj4KPiAgLyoKPiBAQCAtNTEwLDMzICs1MDgsNiBAQCBz dGF0aWMgaW5saW5lIGJvb2wgc3lzdGVtX3N1cHBvcnRzX3N2ZSh2b2lkKQo+ICAJCWNwdXNfaGF2 ZV9jb25zdF9jYXAoQVJNNjRfU1ZFKTsKPiAgfQo+Cj4gLS8qCj4gLSAqIFJlYWQgdGhlIHBzZXVk by1aQ1IgdXNlZCBieSBjcHVmZWF0dXJlcyB0byBpZGVudGlmeSB0aGUgc3VwcG9ydGVkIFNWRQo+ IC0gKiB2ZWN0b3IgbGVuZ3RoLgo+IC0gKgo+IC0gKiBVc2Ugb25seSBpZiBTVkUgaXMgcHJlc2Vu dC4KPiAtICogVGhpcyBmdW5jdGlvbiBjbG9iYmVycyB0aGUgU1ZFIHZlY3RvciBsZW5ndGguCj4g LSAqLwo+IC1zdGF0aWMgaW5saW5lIHU2NCByZWFkX3pjcl9mZWF0dXJlcyh2b2lkKQo+IC17Cj4g LQl1NjQgemNyOwo+IC0JdW5zaWduZWQgaW50IHZxX21heDsKPiAtCj4gLQkvKgo+IC0JICogU2V0 IHRoZSBtYXhpbXVtIHBvc3NpYmxlIFZMLCBhbmQgd3JpdGUgemVyb2VzIHRvIGFsbCBvdGhlcgo+ IC0JICogYml0cyB0byBzZWUgaWYgdGhleSBzdGljay4KPiAtCSAqLwo+IC0Jc3ZlX2tlcm5lbF9l bmFibGUoTlVMTCk7Cj4gLQl3cml0ZV9zeXNyZWdfcyhaQ1JfRUx4X0xFTl9NQVNLLCBTWVNfWkNS X0VMMSk7Cj4gLQo+IC0JemNyID0gcmVhZF9zeXNyZWdfcyhTWVNfWkNSX0VMMSk7Cj4gLQl6Y3Ig Jj0gfih1NjQpWkNSX0VMeF9MRU5fTUFTSzsgLyogZmluZCBzdGlja3kgMXMgb3V0c2lkZSBMRU4g ZmllbGQgKi8KPiAtCXZxX21heCA9IHN2ZV92cV9mcm9tX3ZsKHN2ZV9nZXRfdmwoKSk7Cj4gLQl6 Y3IgfD0gdnFfbWF4IC0gMTsgLyogc2V0IExFTiBmaWVsZCB0byBtYXhpbXVtIGVmZmVjdGl2ZSB2 YWx1ZSAqLwo+IC0KPiAtCXJldHVybiB6Y3I7Cj4gLX0KPiAtCj4gICNlbmRpZiAvKiBfX0FTU0VN QkxZX18gKi8KPgo+ICAjZW5kaWYKPiBkaWZmIC0tZ2l0IGEvYXJjaC9hcm02NC9pbmNsdWRlL2Fz bS9mcHNpbWQuaCBiL2FyY2gvYXJtNjQvaW5jbHVkZS9hc20vZnBzaW1kLmgKPiBpbmRleCAzZTAw ZjcwLi5mYjYwYjIyIDEwMDY0NAo+IC0tLSBhL2FyY2gvYXJtNjQvaW5jbHVkZS9hc20vZnBzaW1k LmgKPiArKysgYi9hcmNoL2FybTY0L2luY2x1ZGUvYXNtL2Zwc2ltZC5oCj4gQEAgLTY5LDYgKzY5 LDggQEAgZXh0ZXJuIHVuc2lnbmVkIGludCBzdmVfZ2V0X3ZsKHZvaWQpOwo+ICBzdHJ1Y3QgYXJt NjRfY3B1X2NhcGFiaWxpdGllczsKPiAgZXh0ZXJuIHZvaWQgc3ZlX2tlcm5lbF9lbmFibGUoY29u c3Qgc3RydWN0IGFybTY0X2NwdV9jYXBhYmlsaXRpZXMgKl9fdW51c2VkKTsKPgo+ICtleHRlcm4g dTY0IHJlYWRfemNyX2ZlYXR1cmVzKHZvaWQpOwo+ICsKPiAgZXh0ZXJuIGludCBfX3JvX2FmdGVy X2luaXQgc3ZlX21heF92bDsKPgo+ICAjaWZkZWYgQ09ORklHX0FSTTY0X1NWRQo+IGRpZmYgLS1n aXQgYS9hcmNoL2FybTY0L2luY2x1ZGUvYXNtL3Byb2Nlc3Nvci5oIGIvYXJjaC9hcm02NC9pbmNs dWRlL2FzbS9wcm9jZXNzb3IuaAo+IGluZGV4IDc2NzU5ODkuLmY5MDJiNmQgMTAwNjQ0Cj4gLS0t IGEvYXJjaC9hcm02NC9pbmNsdWRlL2FzbS9wcm9jZXNzb3IuaAo+ICsrKyBiL2FyY2gvYXJtNjQv aW5jbHVkZS9hc20vcHJvY2Vzc29yLmgKPiBAQCAtNDAsNiArNDAsNyBAQAo+Cj4gICNpbmNsdWRl IDxhc20vYWx0ZXJuYXRpdmUuaD4KPiAgI2luY2x1ZGUgPGFzbS9jcHVmZWF0dXJlLmg+Cj4gKyNp bmNsdWRlIDxhc20vZnBzaW1kLmg+Cj4gICNpbmNsdWRlIDxhc20vaHdfYnJlYWtwb2ludC5oPgo+ ICAjaW5jbHVkZSA8YXNtL2xzZS5oPgo+ICAjaW5jbHVkZSA8YXNtL3BndGFibGUtaHdkZWYuaD4K PiBkaWZmIC0tZ2l0IGEvYXJjaC9hcm02NC9rZXJuZWwvZnBzaW1kLmMgYi9hcmNoL2FybTY0L2tl cm5lbC9mcHNpbWQuYwo+IGluZGV4IGRlZDdmZmQuLjUxNTJiYmMgMTAwNjQ0Cj4gLS0tIGEvYXJj aC9hcm02NC9rZXJuZWwvZnBzaW1kLmMKPiArKysgYi9hcmNoL2FybTY0L2tlcm5lbC9mcHNpbWQu Ywo+IEBAIC0zNyw2ICszNyw3IEBACj4gICNpbmNsdWRlIDxsaW51eC9zY2hlZC90YXNrX3N0YWNr Lmg+Cj4gICNpbmNsdWRlIDxsaW51eC9zaWduYWwuaD4KPiAgI2luY2x1ZGUgPGxpbnV4L3NsYWIu aD4KPiArI2luY2x1ZGUgPGxpbnV4L3N0ZGRlZi5oPgo+ICAjaW5jbHVkZSA8bGludXgvc3lzY3Rs Lmg+Cj4KPiAgI2luY2x1ZGUgPGFzbS9lc3IuaD4KPiBAQCAtNzU0LDYgKzc1NSwzMyBAQCB2b2lk IHN2ZV9rZXJuZWxfZW5hYmxlKGNvbnN0IHN0cnVjdCBhcm02NF9jcHVfY2FwYWJpbGl0aWVzICpf X2Fsd2F5c191bnVzZWQgcCkKPiAgCWlzYigpOwo+ICB9Cj4KPiArLyoKPiArICogUmVhZCB0aGUg cHNldWRvLVpDUiB1c2VkIGJ5IGNwdWZlYXR1cmVzIHRvIGlkZW50aWZ5IHRoZSBzdXBwb3J0ZWQg U1ZFCj4gKyAqIHZlY3RvciBsZW5ndGguCj4gKyAqCj4gKyAqIFVzZSBvbmx5IGlmIFNWRSBpcyBw cmVzZW50Lgo+ICsgKiBUaGlzIGZ1bmN0aW9uIGNsb2JiZXJzIHRoZSBTVkUgdmVjdG9yIGxlbmd0 aC4KPiArICovCj4gK3U2NCByZWFkX3pjcl9mZWF0dXJlcyh2b2lkKQo+ICt7Cj4gKwl1NjQgemNy Owo+ICsJdW5zaWduZWQgaW50IHZxX21heDsKPiArCj4gKwkvKgo+ICsJICogU2V0IHRoZSBtYXhp bXVtIHBvc3NpYmxlIFZMLCBhbmQgd3JpdGUgemVyb2VzIHRvIGFsbCBvdGhlcgo+ICsJICogYml0 cyB0byBzZWUgaWYgdGhleSBzdGljay4KPiArCSAqLwo+ICsJc3ZlX2tlcm5lbF9lbmFibGUoTlVM TCk7Cj4gKwl3cml0ZV9zeXNyZWdfcyhaQ1JfRUx4X0xFTl9NQVNLLCBTWVNfWkNSX0VMMSk7Cj4g Kwo+ICsJemNyID0gcmVhZF9zeXNyZWdfcyhTWVNfWkNSX0VMMSk7Cj4gKwl6Y3IgJj0gfih1NjQp WkNSX0VMeF9MRU5fTUFTSzsgLyogZmluZCBzdGlja3kgMXMgb3V0c2lkZSBMRU4gZmllbGQgKi8K PiArCXZxX21heCA9IHN2ZV92cV9mcm9tX3ZsKHN2ZV9nZXRfdmwoKSk7Cj4gKwl6Y3IgfD0gdnFf bWF4IC0gMTsgLyogc2V0IExFTiBmaWVsZCB0byBtYXhpbXVtIGVmZmVjdGl2ZSB2YWx1ZSAqLwo+ ICsKPiArCXJldHVybiB6Y3I7Cj4gK30KPiArCj4gIHZvaWQgX19pbml0IHN2ZV9zZXR1cCh2b2lk KQo+ICB7Cj4gIAl1NjQgemNyOwo+IGRpZmYgLS1naXQgYS9hcmNoL2FybTY0L2tlcm5lbC9wdHJh Y2UuYyBiL2FyY2gvYXJtNjQva2VybmVsL3B0cmFjZS5jCj4gaW5kZXggN2ZmODFmZS4uNzg4ODlj NCAxMDA2NDQKPiAtLS0gYS9hcmNoL2FybTY0L2tlcm5lbC9wdHJhY2UuYwo+ICsrKyBiL2FyY2gv YXJtNjQva2VybmVsL3B0cmFjZS5jCj4gQEAgLTQ0LDYgKzQ0LDcgQEAKPiAgI2luY2x1ZGUgPGFz bS9jb21wYXQuaD4KPiAgI2luY2x1ZGUgPGFzbS9jcHVmZWF0dXJlLmg+Cj4gICNpbmNsdWRlIDxh c20vZGVidWctbW9uaXRvcnMuaD4KPiArI2luY2x1ZGUgPGFzbS9mcHNpbWQuaD4KPiAgI2luY2x1 ZGUgPGFzbS9wZ3RhYmxlLmg+Cj4gICNpbmNsdWRlIDxhc20vc3RhY2t0cmFjZS5oPgo+ICAjaW5j bHVkZSA8YXNtL3N5c2NhbGwuaD4KCgotLQpBbGV4IEJlbm7DqWUKCl9fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmxpbnV4LWFybS1rZXJuZWwgbWFpbGluZyBs aXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5m cmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LWFybS1rZXJuZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 From: alex.bennee@linaro.org (Alex =?utf-8?Q?Benn=C3=A9e?=) Date: Thu, 24 May 2018 11:12:09 +0100 Subject: [PATCH v10 11/18] arm64/sve: Move read_zcr_features() out of cpufeature.h In-Reply-To: <1527005119-6842-12-git-send-email-Dave.Martin@arm.com> References: <1527005119-6842-1-git-send-email-Dave.Martin@arm.com> <1527005119-6842-12-git-send-email-Dave.Martin@arm.com> Message-ID: <87603dtlae.fsf@linaro.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Dave Martin writes: > Having read_zcr_features() inline in cpufeature.h results in that > header requiring #includes which make it hard to include > elsewhere without triggering header inclusion > cycles. > > This is not a hot-path function and arguably should not be in > cpufeature.h in the first place, so this patch moves it to > fpsimd.c, compiled conditionally if CONFIG_ARM64_SVE=y. > > This allows some SVE-related #includes to be dropped from > cpufeature.h, which will ease future maintenance. > > A couple of missing #includes of are exposed by this > change under arch/arm64/. This patch adds the missing #includes as > necessary. > > No functional change. > > Signed-off-by: Dave Martin > Acked-by: Catalin Marinas > Acked-by: Marc Zyngier Reviewed-by: Alex Benn?e > --- > arch/arm64/include/asm/cpufeature.h | 29 ----------------------------- > arch/arm64/include/asm/fpsimd.h | 2 ++ > arch/arm64/include/asm/processor.h | 1 + > arch/arm64/kernel/fpsimd.c | 28 ++++++++++++++++++++++++++++ > arch/arm64/kernel/ptrace.c | 1 + > 5 files changed, 32 insertions(+), 29 deletions(-) > > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h > index 09b0f2a..0a6b713 100644 > --- a/arch/arm64/include/asm/cpufeature.h > +++ b/arch/arm64/include/asm/cpufeature.h > @@ -11,9 +11,7 @@ > > #include > #include > -#include > #include > -#include > #include > > /* > @@ -510,33 +508,6 @@ static inline bool system_supports_sve(void) > cpus_have_const_cap(ARM64_SVE); > } > > -/* > - * Read the pseudo-ZCR used by cpufeatures to identify the supported SVE > - * vector length. > - * > - * Use only if SVE is present. > - * This function clobbers the SVE vector length. > - */ > -static inline u64 read_zcr_features(void) > -{ > - u64 zcr; > - unsigned int vq_max; > - > - /* > - * Set the maximum possible VL, and write zeroes to all other > - * bits to see if they stick. > - */ > - sve_kernel_enable(NULL); > - write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL1); > - > - zcr = read_sysreg_s(SYS_ZCR_EL1); > - zcr &= ~(u64)ZCR_ELx_LEN_MASK; /* find sticky 1s outside LEN field */ > - vq_max = sve_vq_from_vl(sve_get_vl()); > - zcr |= vq_max - 1; /* set LEN field to maximum effective value */ > - > - return zcr; > -} > - > #endif /* __ASSEMBLY__ */ > > #endif > diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h > index 3e00f70..fb60b22 100644 > --- a/arch/arm64/include/asm/fpsimd.h > +++ b/arch/arm64/include/asm/fpsimd.h > @@ -69,6 +69,8 @@ extern unsigned int sve_get_vl(void); > struct arm64_cpu_capabilities; > extern void sve_kernel_enable(const struct arm64_cpu_capabilities *__unused); > > +extern u64 read_zcr_features(void); > + > extern int __ro_after_init sve_max_vl; > > #ifdef CONFIG_ARM64_SVE > diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h > index 7675989..f902b6d 100644 > --- a/arch/arm64/include/asm/processor.h > +++ b/arch/arm64/include/asm/processor.h > @@ -40,6 +40,7 @@ > > #include > #include > +#include > #include > #include > #include > diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c > index ded7ffd..5152bbc 100644 > --- a/arch/arm64/kernel/fpsimd.c > +++ b/arch/arm64/kernel/fpsimd.c > @@ -37,6 +37,7 @@ > #include > #include > #include > +#include > #include > > #include > @@ -754,6 +755,33 @@ void sve_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p) > isb(); > } > > +/* > + * Read the pseudo-ZCR used by cpufeatures to identify the supported SVE > + * vector length. > + * > + * Use only if SVE is present. > + * This function clobbers the SVE vector length. > + */ > +u64 read_zcr_features(void) > +{ > + u64 zcr; > + unsigned int vq_max; > + > + /* > + * Set the maximum possible VL, and write zeroes to all other > + * bits to see if they stick. > + */ > + sve_kernel_enable(NULL); > + write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL1); > + > + zcr = read_sysreg_s(SYS_ZCR_EL1); > + zcr &= ~(u64)ZCR_ELx_LEN_MASK; /* find sticky 1s outside LEN field */ > + vq_max = sve_vq_from_vl(sve_get_vl()); > + zcr |= vq_max - 1; /* set LEN field to maximum effective value */ > + > + return zcr; > +} > + > void __init sve_setup(void) > { > u64 zcr; > diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c > index 7ff81fe..78889c4 100644 > --- a/arch/arm64/kernel/ptrace.c > +++ b/arch/arm64/kernel/ptrace.c > @@ -44,6 +44,7 @@ > #include > #include > #include > +#include > #include > #include > #include -- Alex Benn?e