diff for duplicates of <8760dh5cbl.fsf@linaro.org> diff --git a/a/1.txt b/N1/1.txt index a938628..a4b108e 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -143,3 +143,7 @@ Constrains the scalable vector register length for EL1 and EL0 to (LEN+1)x128 bi >> [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF", >> [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)", >> [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)", + + +-- +Alex Bennée diff --git a/a/content_digest b/N1/content_digest index fa78095..a04a566 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -160,6 +160,10 @@ ">> +\t[ESR_ELx_EC_SVE]\t\t= \"SVE\",\n" ">> \t[ESR_ELx_EC_IMP_DEF]\t\t= \"EL3 IMP DEF\",\n" ">> \t[ESR_ELx_EC_IABT_LOW]\t\t= \"IABT (lower EL)\",\n" - ">> \t[ESR_ELx_EC_IABT_CUR]\t\t= \"IABT (current EL)\"," + ">> \t[ESR_ELx_EC_IABT_CUR]\t\t= \"IABT (current EL)\",\n" + "\n" + "\n" + "--\n" + "Alex Benn\303\251e" -5fcf3993f9e5a2037beca4fca494582476ef6854bbfd4c81ee398c60a95e0042 +eaf356ed7e2bb43458fb67886f3dca3ca1c847e14381ac8de17feaecdf413a72
diff --git a/a/1.txt b/N2/1.txt index a938628..7796cee 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,5 +1,5 @@ -Alex Bennée <alex.bennee@linaro.org> writes: +Alex Benn?e <alex.bennee@linaro.org> writes: > Dave Martin <Dave.Martin@arm.com> writes: > @@ -143,3 +143,7 @@ Constrains the scalable vector register length for EL1 and EL0 to (LEN+1)x128 bi >> [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF", >> [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)", >> [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)", + + +-- +Alex Benn?e diff --git a/a/content_digest b/N2/content_digest index fa78095..69ec214 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,23 +1,14 @@ "ref\01502280338-23002-1-git-send-email-Dave.Martin@arm.com\0" "ref\01502280338-23002-7-git-send-email-Dave.Martin@arm.com\0" "ref\087a82t5kos.fsf@linaro.org\0" - "From\0Alex Benn\303\251e <alex.bennee@linaro.org>\0" - "Subject\0Re: [PATCH 06/27] arm64/sve: System register and exception syndrome definitions\0" + "From\0alex.bennee@linaro.org (Alex Benn\303\251e)\0" + "Subject\0[PATCH 06/27] arm64/sve: System register and exception syndrome definitions\0" "Date\0Mon, 21 Aug 2017 13:34:38 +0100\0" - "To\0Dave Martin <Dave.Martin@arm.com>\0" - "Cc\0linux-arm-kernel@lists.infradead.org" - linux-arch@vger.kernel.org - libc-alpha@sourceware.org - Ard Biesheuvel <ard.biesheuvel@linaro.org> - Szabolcs Nagy <szabolcs.nagy@arm.com> - Catalin Marinas <catalin.marinas@arm.com> - Will Deacon <will.deacon@arm.com> - Richard Sandiford <richard.sandiford@arm.com> - " kvmarm@lists.cs.columbia.edu\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "\n" - "Alex Benn\303\251e <alex.bennee@linaro.org> writes:\n" + "Alex Benn?e <alex.bennee@linaro.org> writes:\n" "\n" "> Dave Martin <Dave.Martin@arm.com> writes:\n" ">\n" @@ -160,6 +151,10 @@ ">> +\t[ESR_ELx_EC_SVE]\t\t= \"SVE\",\n" ">> \t[ESR_ELx_EC_IMP_DEF]\t\t= \"EL3 IMP DEF\",\n" ">> \t[ESR_ELx_EC_IABT_LOW]\t\t= \"IABT (lower EL)\",\n" - ">> \t[ESR_ELx_EC_IABT_CUR]\t\t= \"IABT (current EL)\"," + ">> \t[ESR_ELx_EC_IABT_CUR]\t\t= \"IABT (current EL)\",\n" + "\n" + "\n" + "--\n" + Alex Benn?e -5fcf3993f9e5a2037beca4fca494582476ef6854bbfd4c81ee398c60a95e0042 +e2e1659d73bc88b811583a823df72cafc04221d76ce4e721c91f7a076feb3569
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