From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id d14sm3930266wmd.19.2017.01.27.05.44.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jan 2017 05:44:12 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTPS id 3C62D3E008E; Fri, 27 Jan 2017 13:44:12 +0000 (GMT) References: <1485285380-10565-1-git-send-email-peter.maydell@linaro.org> <1485285380-10565-7-git-send-email-peter.maydell@linaro.org> User-agent: mu4e 0.9.19; emacs 25.1.91.4 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org, Liviu Ionescu Subject: Re: [PATCH 06/10] armv7m: set CFSR.UNDEFINSTR on undefined instructions In-reply-to: <1485285380-10565-7-git-send-email-peter.maydell@linaro.org> Date: Fri, 27 Jan 2017 13:44:12 +0000 Message-ID: <8760l0aa8j.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-TUID: oBrU8R4bwuQJ Peter Maydell writes: > From: Michael Davidsaver > > When we take an exception for an undefined instruction, set the > appropriate CFSR bit. > > Signed-off-by: Michael Davidsaver > [PMM: tweaked commit message, comment] > Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée > --- > target/arm/helper.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 7dc30f5..e6b1c36 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6072,6 +6072,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) > switch (cs->exception_index) { > case EXCP_UDEF: > armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); > + env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK; > return; > case EXCP_SWI: > /* The PC already points to the next instruction. */ -- Alex Bennée From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60876) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cX6p5-0003WO-QQ for qemu-devel@nongnu.org; Fri, 27 Jan 2017 08:44:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cX6p5-0003CO-0A for qemu-devel@nongnu.org; Fri, 27 Jan 2017 08:44:15 -0500 Received: from mail-wm0-x22e.google.com ([2a00:1450:400c:c09::22e]:37221) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cX6p4-0003C7-Qd for qemu-devel@nongnu.org; Fri, 27 Jan 2017 08:44:14 -0500 Received: by mail-wm0-x22e.google.com with SMTP id c206so138402978wme.0 for ; Fri, 27 Jan 2017 05:44:14 -0800 (PST) References: <1485285380-10565-1-git-send-email-peter.maydell@linaro.org> <1485285380-10565-7-git-send-email-peter.maydell@linaro.org> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1485285380-10565-7-git-send-email-peter.maydell@linaro.org> Date: Fri, 27 Jan 2017 13:44:12 +0000 Message-ID: <8760l0aa8j.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH 06/10] armv7m: set CFSR.UNDEFINSTR on undefined instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org, Liviu Ionescu Peter Maydell writes: > From: Michael Davidsaver > > When we take an exception for an undefined instruction, set the > appropriate CFSR bit. > > Signed-off-by: Michael Davidsaver > [PMM: tweaked commit message, comment] > Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée > --- > target/arm/helper.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 7dc30f5..e6b1c36 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6072,6 +6072,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) > switch (cs->exception_index) { > case EXCP_UDEF: > armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); > + env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK; > return; > case EXCP_SWI: > /* The PC already points to the next instruction. */ -- Alex Bennée