From: Andi Kleen <andi@firstfloor.org>
To: Manuel Selva <manuel.selva@insa-lyon.fr>
Cc: linux-perf-users@vger.kernel.org
Subject: Re: Link between Intel documentation events and perf list events
Date: Mon, 01 Jul 2013 20:55:39 -0700 [thread overview]
Message-ID: <8761wt62f8.fsf@tassilo.jf.intel.com> (raw)
In-Reply-To: <51D1AA04.7060403@insa-lyon.fr> (Manuel Selva's message of "Mon, 01 Jul 2013 18:10:44 +0200")
Manuel Selva <manuel.selva@insa-lyon.fr> writes:
> My question is about the link between events reported in Intel
> documentation and events listed by perf list. Is the perf list
> cache-misses event the same than the one mentioned as Last-level cache
> missesin Intel documentation ?
Yes it is
(at least currently, perf events are not particularly well defined
and have changed in the past. However this one is proably not likely
to change)
-Andi
--
ak@linux.intel.com -- Speaking for myself only
next prev parent reply other threads:[~2013-07-02 3:55 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-01 16:10 Link between Intel documentation events and perf list events Manuel Selva
2013-07-02 3:55 ` Andi Kleen [this message]
2013-07-02 7:53 ` Manuel Selva
2013-07-02 12:39 ` Andreas Hollmann
2013-07-02 13:33 ` Manuel Selva
2013-07-02 14:49 ` Andi Kleen
2013-07-03 9:06 ` Manuel Selva
2013-07-03 13:28 ` Andi Kleen
2013-07-03 14:02 ` Manuel Selva
[not found] ` <51D28568.8070904@insa-lyon.fr>
2013-07-02 14:41 ` Andi Kleen
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