From mboxrd@z Thu Jan  1 00:00:00 1970
From: Eric Anholt <eric@anholt.net>
Subject: Re: intel graphics performance thought
Date: Tue, 26 Oct 2010 09:45:21 -0700
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To: Peter Clifton <pcjc2@cam.ac.uk>, "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
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On Tue, 26 Oct 2010 04:35:33 +0100, Peter Clifton <pcjc2@cam.ac.uk> wrote:
> On Mon, 2010-10-25 at 12:44 -0700, Eric Anholt wrote:
>=20
> > So, what if the problem is that our URB allocations aren't big enough?
> > I would expect that to look kind of like what I'm seeing.  One
> > experiment would be to go double the preferred size of each stage in
> > brw_urb.c one by one -- is one stage's URB allocation a limit?  Or, am I
> > on the right track at all (go reduce all the preferred sizes to 1/2 and
> > see if that hurts)?
>
> I think what we really need for better understanding is a per-frame
> profile of when different execution units are busy. It sounds like you
> have something like this in development for Ironlake (unfortunately I'm
> only on GM45 here).

Sadly, it's nothing that awesome. Just like intel_gpu_top, but a
different set of bits.

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