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From: Miles Glenn To: Chinmay Rath , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com Date: Mon, 24 Aug 2026 09:39:44 -0500 In-Reply-To: <20260820140114.327023-14-rathc@linux.ibm.com> References: <20260820140114.327023-1-rathc@linux.ibm.com> <20260820140114.327023-14-rathc@linux.ibm.com> Organization: IBM Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-27.el8_10) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-GUID: xsSdzCycKTOeDiBGS2veCsiXE7eODOzJ X-Proofpoint-ORIG-GUID: UDsGzEZwAmk_j6PCuTZ4zCGmcqUqDTHU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI0MDEyMiBTYWx0ZWRfXy475ARc5/IQn FrzEqgAyR1LDFW+l1yMIvScaHmg+odJtkENP9JdiDU0ei+8wO+0QMOBPPqqlXa+zBG/cE0Kd4HY hX/1rs5VzjYtYD07Kr8u8TP6ZBQ/nvBGjZxgugz98Pmqas9M1sJW3M07BHGoe7Qg+JVLmE1ZAft +bQvzLo98F42RhqDnbiXXAw6c2Bwj6FtociJCQxo/nRWqVWxq8DSTKi1OOE1Ez69YmsDiLSLxEw z4+jBDM8cUt3FrhzaxjoQBdWaLANscKDhSy63uBbTjFLUxUy/R0pRBTKj5vdHZpv1u5zCtOZAmG lLZ/Ru2xBKTgzYTKoG8oBlf9bK9BBhC7AO2FUtc4Cd4frvqli6RNp7zmC1nQPycADuCOytpVT3P bK7yq81NHMgPXBZN6a9WdwWUPHdbMUieYxC8YEdCQrr/Eqxb4Q+O4roEE3ZZqN0X4D3OMEZxYrT W91eP7/X2L9ost/qLMA== X-Authority-Analysis: v=2.4 cv=QsRuG1yd c=1 sm=1 tr=0 ts=6a8c57b5 cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=VnNF1IyMAAAA:8 a=1VKqNc-gu6NC59ff_LEA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI0MDEyMiBTYWx0ZWRfX4/oydoFhymYE BrioGFjwsM9SA2VveNs236DQiMHXAUpEcsa2dh9mnml95aT9rEEIKv7lHL5fwAUlqxqUXIKBj/h hsQy0y9Lt5wSzW++Lw0w3iGVKndGBEg= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-24_04,2026-08-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608240122 Received-SPF: pass client-ip=148.163.156.1; envelope-from=milesg@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: milesg@linux.ibm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Glenn Miles Thanks, Glenn On Thu, 2026-08-20 at 19:30 +0530, Chinmay Rath wrote: > From: Ojaswin Mujoo > > Moving the following instructions to decodetree specification : > isync > > The changes were verified by validating that the tcg ops generated by > those instructions remain the same, which were captured with the '-d > in_asm,op' flag. > > Signed-off-by: Ojaswin Mujoo > Reviewed-by: Nikhil Kumar Singh > Signed-off-by: Chinmay Rath > --- > target/ppc/insn32.decode | 1 + > target/ppc/translate.c | 15 --------------- > target/ppc/translate/storage-ctrl-impl.c.inc | 17 +++++++++++++++++ > 3 files changed, 18 insertions(+), 15 deletions(-) > > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > index a1c2f549bd..91ece88a70 100644 > --- a/target/ppc/insn32.decode > +++ b/target/ppc/insn32.decode > @@ -1472,6 +1472,7 @@ MSGSYNC 011111 ----- ----- ----- 1101110110 - > @X_sync ...... .. l:3 ... sc:2 ..... .......... . &X_sync > SYNC 011111 -- ... --- .. ----- 1001010110 - @X_sync > EIEIO 011111 ----- ----- ----- 1101010110 - > +ISYNC 010011 ----- ----- ----- 0010010110 - > > # Condition Register Field Instruction > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 179cb69dc5..a31cda4490 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -2727,20 +2727,6 @@ static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) > static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } > #endif > > -/* isync */ > -static void gen_isync(DisasContext *ctx) > -{ > - /* > - * We need to check for a pending TLB flush. This can only happen in > - * kernel mode however so check MSR_PR > - */ > - if (!ctx->pr) { > - gen_check_tlb_flush(ctx, false); > - } > - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); > - ctx->base.is_jmp = DISAS_EXIT_UPDATE; > -} > - > /* wait */ > static void gen_wait(DisasContext *ctx) > { > @@ -5377,7 +5363,6 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), > GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), > GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), > GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), > -GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), > /* ISA v3.0 changed the extended opcode from 62 to 30 */ > GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), > GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), > diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc > index b8b4454663..943229c438 100644 > --- a/target/ppc/translate/storage-ctrl-impl.c.inc > +++ b/target/ppc/translate/storage-ctrl-impl.c.inc > @@ -155,6 +155,23 @@ static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE *a) > return true; > } > > +static bool trans_ISYNC(DisasContext *ctx, arg_ISYNC *a) > +{ > + REQUIRE_INSNS_FLAGS(ctx, MEM); > + > + /* > + * We need to check for a pending TLB flush. This can only happen in > + * kernel mode however so check MSR_PR > + */ > + if (!ctx->pr) { > + gen_check_tlb_flush(ctx, false); > + } > + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); > + ctx->base.is_jmp = DISAS_EXIT_UPDATE; > + > + return true; > +} > + > static bool trans_SLBSYNC(DisasContext *ctx, arg_SLBSYNC *a) > { > REQUIRE_64BIT(ctx);