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Fri, 30 Oct 2026 09:43:13 -0700 (PDT) Received: from draig.lan ([185.124.0.158]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4aa8213ead6sm145917035e9.14.2026.10.30.09.43.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Oct 2026 09:43:12 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 2920E5F7FD; Fri, 30 Oct 2026 16:43:12 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Peter Maydell Cc: qemu-devel@nongnu.org, Paolo Bonzini , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Richard Henderson , qemu-arm@nongnu.org Subject: Re: [PATCH 3/4] target/arm: simplify wfxt_timer_cb to only trigger cpu_interrupt In-Reply-To: (Peter Maydell's message of "Fri, 30 Oct 2026 14:41:47 +0000") References: <20261030141046.2710206-1-alex.bennee@linaro.org> <20261030141046.2710206-4-alex.bennee@linaro.org> User-Agent: mu4e 1.14.4; emacs 30.1 Date: Fri, 30 Oct 2026 16:43:12 +0000 Message-ID: <877biz87hb.fsf@draig.linaro.org> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-10.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Peter Maydell writes: > On Fri, 30 Oct 2026 at 14:10, Alex Benn=C3=A9e w= rote: >> >> HALT_WFE will always be cleared when leaving halt via >> arm_cpu_leaving_halt so we don't need to worry about atomic games in >> the asynchronous timer callback. Furthermore, a WFET timeout or >> event-stream expiration is not an event that sets the event register; > > No, this is still not true. WFET timeouts don't set the > event register, but event-stream expiration does. Oops I missed that comment, how about something like this: --8<---------------cut here---------------start------------->8--- modified target/arm/cpu.h @@ -984,8 +984,12 @@ struct ArchCPU { * pmu_op_finish() - it does not need other handling during migration */ QEMUTimer *pmu_timer; - /* Timer used for WFxT timeouts OR event stream events */ + /* + * Timer used for WFxT timeouts OR event stream events, + * wfxt_triggers_event set depending on what will come first. + */ QEMUTimer *wfxt_timer; + bool wfxt_triggers_event; =20 /* GPIO outputs for generic timer */ qemu_irq gt_timer_outputs[NUM_GTIMERS]; modified target/arm/cpu.c @@ -885,26 +885,17 @@ static void arm_cpu_leaving_halt(CPUState *cs) } #endif =20 -/* - * Unlike almost everything else that messes with the halt_reason and - * event_register details the timer callbacks are not in the vCPU - * context. - * - * To prevent races we atomically consume a HALT_WFE and set the event - * register. Either way we trigger the an exit event. - */ static void arm_wfxt_timer_cb(void *opaque) { ARMCPU *cpu =3D opaque; CPUState *cs =3D CPU(cpu); CPUARMState *env =3D &cpu->env; =20 - if (qatomic_cmpxchg(&env->halt_reason, HALT_WFE, NOT_HALTED)) { + if (cpu->wfxt_triggers_event) { qatomic_set(&env->event_register, true); } - /* - * We expect the CPU to be halted; this will cause arm_cpu_is_work() + * We expect the CPU to be halted; this will cause arm_cpu_has_work() * to return true (so we will come out of halt even with no other * pending interrupt), and the TCG accelerator's cpu_exec_interrupt() * function auto-clears the CPU_INTERRUPT_EXITTB flag for us. modified target/arm/tcg/op_helper.c @@ -377,6 +377,7 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) return; #else CPUState *cs =3D env_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint32_t excp; int target_el =3D check_wfx_trap(env, false, &excp); =20 @@ -398,6 +399,7 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) target_el); } =20 + cpu->wfxt_triggers_event =3D false; qatomic_set(&env->halt_reason, HALT_WFI); cs->exception_index =3D EXCP_HLT; cs->halted =3D 1; @@ -461,6 +463,7 @@ void HELPER(wfit)(CPUARMState *env, uint32_t rd) } else { timer_mod(cpu->wfxt_timer, nexttick); } + cpu->wfxt_triggers_event =3D false; qatomic_set(&env->halt_reason, HALT_WFI); cs->exception_index =3D EXCP_HLT; cs->halted =3D 1; @@ -720,12 +723,14 @@ void HELPER(wfet)(CPUARMState *env, uint32_t rd) next_event =3D gt_calc_next_event_stream(env); if (next_event > 0 && next_event < nexttick) { timer_mod(cpu->wfxt_timer, next_event); + cpu->wfxt_triggers_event =3D true; } else { if (nexttick =3D=3D INT64_MAX) { timer_mod_ns(cpu->wfxt_timer, INT64_MAX); } else { timer_mod(cpu->wfxt_timer, nexttick); } + cpu->wfxt_triggers_event =3D false; } =20 qatomic_set(&env->halt_reason, HALT_WFE); --8<---------------cut here---------------end--------------->8--- > > -- PMM --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro