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From: Thomas Gleixner <tglx@kernel.org>
To: Melody Wang <huibo.wang@amd.com>, x86@kernel.org
Cc: LKML <linux-kernel@vger.kernel.org>, Melody Wang <huibo.wang@amd.com>
Subject: Re: [PATCH] x86/apic: Ensure ICR register write value is handled as 32 bits
Date: Mon, 20 Jul 2026 20:41:05 +0200	[thread overview]
Message-ID: <877bmpmrlq.ffs@fw13> (raw)
In-Reply-To: <20260708012117.177959-1-huibo.wang@amd.com>

On Wed, Jul 08 2026 at 01:21, Melody Wang wrote:
> The low 32-bit ICR data is prepared by __prepare_ICR(), which returns
> a 32-bit value. However, when this value is assigned to a new variable,
> it's easy to mistakenly declare that variable with a different width.
>
> To avoid this class of mistakes, use __prepare_ICR() directly as the
> function argument instead of storing its result in an intermediate
> variable. This also shaves off a bunch of lines in the code.
>
> There should be no functionality change resulting from this patch.
>
> Signed-off-by: Melody Wang <huibo.wang@amd.com>

Acked-by: Thomas Gleixner <tglx@kernel.org>

  reply	other threads:[~2026-07-20 18:41 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-08  1:21 [PATCH] x86/apic: Ensure ICR register write value is handled as 32 bits Melody Wang
2026-07-20 18:41 ` Thomas Gleixner [this message]
2026-07-20 19:27 ` [tip: x86/cleanups] " tip-bot2 for Melody Wang

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