From: "Alex Bennée" <alex.bennee@linaro.org>
To: Nikita Shubin <nikita.shubin@maquefel.me>
Cc: qemu-devel@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [PATCH 1/2] semihosting/arm-compat-semi: Fix auto‑strlen detection for 32‑bit targets
Date: Tue, 23 Jun 2026 13:40:21 +0100 [thread overview]
Message-ID: <877bnpmnuy.fsf@draig.linaro.org> (raw)
In-Reply-To: <20260619-fix-sign-extended-32-bit-addresses-v1-1-47ae14f8e8c5@maquefel.me> (Nikita Shubin's message of "Fri, 19 Jun 2026 12:52:19 +0300")
Nikita Shubin <nikita.shubin@maquefel.me> writes:
> The switch from target_ulong to uint64_t broke the mechanism of passing -1
> (0xffffffff) in arg2 to signal validate_strlen() to compute the string
> length automatically. For 32‑bit semihosting, detect when arg2 is
> 0xffffffff and replace it with 0xffffffffffffffff. This causes an overflow
> to zero, restoring the original behavior of automatic length calculation.
>
> Fixes: 6dfbf9b6cfe ("semihosting/arm-compat-semi: replace target_ulong")
> Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
next prev parent reply other threads:[~2026-06-23 12:40 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-19 9:52 [PATCH 0/2] semihosting: Fix auto-strlen for 32-bit targets + add riscv32 test Nikita Shubin
2026-06-19 9:52 ` [PATCH 1/2] semihosting/arm-compat-semi: Fix auto‑strlen detection for 32‑bit targets Nikita Shubin
2026-06-23 12:40 ` Alex Bennée [this message]
2026-06-19 9:52 ` [PATCH 2/2] tests/tcg/riscv32: Add RISC-V 32-bit semihosting test Nikita Shubin
2026-06-22 4:32 ` Alistair Francis
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